This is another interesting aspect of SV, which beginners usually get confused. This is an excellent blog post @ trusser on the same.
Deep vs Shallow Copy in SystemVerilog
Some interesting ways to get a delayed version of signal in SV
In TB world, sometime you will need a signal which is N clock delayed version of another signal. You can do it by using 9 intermediate variables, or use these.
// I want 10 clock delayed version of signal abc
always @(posedge clk) begin
abc_10_clk_delayed_1 <= $past(abc, 10); // This works in vcs
abc_10_clk_delayed_2 <= repeat(10) @(posedge clk) abc;
end
System Verilog `define macros : Why and how to use them (and where not to use!!!)
I most confess, I have become a very big fan of SystemVerilog `define macro for the amount of effort I save because of using it. The big advantage of using this is that you can concisely describe your intention in a more readable (and less SystemVerilog syntax) using macro. Another advantage is you need to change only at one place if you find out that you need to change the expression you have used in 100 of places. The 3rd reason is that it is widely used in industry. Some example worth quoting are
- Using SystemVerilog Assertions for Functional Coverage
- Using SystemVerilog Assertions for Creating Property-Based Checkers
- SystemVerilog Assertions Design Tricks and SVA Bind Files
- VMM and especially VMM data macro
Ans : Web (thanks to the all powerful demi-god of internet ... Google)
- http://www.google.co.in/#hl=en&safe=off&q=Systemverilog+Macro
- System Verilog LRM 3.1a : Section : 25.2
- Sandeep Vaniya's Advanced Use of define macro in SystemVerilog (not so advanced actually !!!)
// Example macro for a coverage class
// Aim : want to get ABC_cp : coverpoint ABC {bins b = {1}; }
// by calling `COV(ABC)
`define COV(__name) __name``_cp : coverpoint __name {bins b = {1}; }
// Next
// What to do if I want cp_ABC in place of ABC_cp as for the above example
// NOTE : I can't use cp_``__name as cp_ is not an input to the macro
// Solution
// Use nested macros
`define PREFIX(__prefix, __name) __prefix``__name
`define COV2(__name) `PREFIX(cp_,__name) : coverpoint __name {bins b = {1}; }
Nested macro is not a new thing in SV. They are being extensively used in VMM data macro class. But no example of nested macro and achieving of addition pre_fix to variable name in `define macro is bit puzzling to me. I tried the above in vcs and seems to work perfectly fine.Next, where not to use `define (SV other better alternatives to `define these cases)
Answers to SystemVerilog Interview Questions - 8
13. What is the difference between mailbox and queue?
Ans:-
Mailbox are FIFO queue, which allows only atomic operations. They can be bounded/unbounded. A bounded mailbox can suspend the thread (while writing if full, while reading if empty) via get/put task. Thats why mailbox is well suited for communication between threads.
24. What is the use of $cast?
Ans:-
Typecasting in SV can be done either via static casting (
27. What is $unit?
Ans:-
Refer these 2 doc form more details
- http://www.systemverilog.org/pdf/SystemVerilog_Overall_31A.pdf
- SV LRM 3.1a :: Section 18.3
28 .What are bi-directional constraints?
Ans:-
Constraints by-default in SystemVerilog are bi-directional. That implies that the constraint solver doesn't follow the sequence in which the constraints are specified. All the variables are looked simultaneously. Even the procedural looking constrains like if ... else ... and -> constrains, both if and else part are tried to solve concurrently. For example (a==0) -> (b==1) shall be solved as all the possible solution of (!(a==0) || (b==1)).
29. What is solve...before constraint ?
Ans:-
In the case where the user want to specify the order in which the constraints solver shall solve the constraints, the user can specify the order via solve before construct. i.e.
...
constraint XYZ {
a inside {[0:100]|;
b < 20;
a + b > 30;
solve a before b;
}
The solution of the constraint doesn't change with solve before construct. But the probability of choosing a particular solution change by it.
40. What is circular dependency and how to avoid this problem ?
Ans:-
Over specifying the solving order might result in circular dependency, for which there is no solution, and the constraint solver might give error/warning or no constraining. Example
...
int x, y, z;
constraint XYZ {
solve x before y;
solve y before z;
solve z before x;
....
}
Answers to SystemVerilog Interview Questions - 7
4. What is the need of clocking blocks ?
Ans:-
Clocking block in SystemVerilog are used for specifying the clock signal, timing, and synchronization requirements of various blocks. It separates the timing related information from structural, functional and procedural element of the TB. There are quite a few links on clocking block in the internet. These are links to learn about SV clocking blocks.
- AsicGuru :: To the point answer on the need of clocking block
- Testbench.in :: Clocking block
- ProjectVeripage :: Clocking block
- Doulos :: Clocking block
- Asicworld :: Clocking block
- SystemVerilog Event Regions, Race Avoidance & Guidelines
5. What are the ways to avoid race condition between testbench and RTL using SystemVerilog?
Ans:-
Short answer : -
- Program block
- Clocking block
- Enforcement of design signals being driven in non-blocking fashion from program block
Too long to describe here :). Please refer these doc/sections for more idea/info
- Section 16.4 of SV LRM
- http://www.testbench.in/SV_24_PROGRAM_BLOCK.html
- http://www.sunburst-design.com/papers/CummingsSNUG2006Boston_SystemVerilog_Events.pdf
- VG discussion of the necessity of program block.
7. What are the types of coverages available in SV ?
Ans:-
Using covergroup : variables, expression, and their cross
Using cover keyword : properties
12. What is the use of the abstract class?
Ans:-
Answers to SystemVerilog Interview Questions - 6
(30)Without using randomize method or rand,generate an array of unique values?
Ans:-
... int UniqVal[10]; foreach(UniqVal[i]) UniqVal[i] = i; UniqVal.shuffle(); ...
(32)What is the difference between byte and bit [7:0]?
Ans:-
byte is signed whereas bit [7:0] is unsigned.
(33)What is the difference between program block and module?
Ans:-
Program block is newly added in SystemVerilog. It serves these purposes
- It separates testbench from DUT
- It helps in ensuring that testbench doesn't have any race condition with DUT
- It provides an entry point for execution of testbench
- It provides syntactic context (via program ... endprogram) that specifies scheduling in the Reactive Region.
- Program blocks can't have always block inside them, modules can have.
- Program blocks can't contain UDP, modules, or other instance of program block inside them. Modules don't have any such restrictions.
- Inside a program block, program variable can only be assigned using blocking assignment and non-program variables can only be assigned using non-blocking assignments. No such restrictions on module
- Program blocks get executed in the re-active region of scheduling queue, module blocks get executed in the active region
- A program can call a task or function in modules or other programs. But a module can not call a task or function in a program.
- http://www.testbench.in/SV_24_PROGRAM_BLOCK.html
- http://www.project-veripage.com/program_blocks_1.php and few more next/next !!!
- Section 16, SystemVerilog LRM 3.1a ... It's worth the effort reading line-by-line (and between the lines if you can :) ).
Ans:-
Modports are part of Interface. Modports are used for specifing the direction of the signals with respect to various modules the interface connects to.
...
interface my_intf;
wire x, y, z;
modport master (input x, y, output z);
modport slave (output x, y, input z);
endinterface
Please refer section 19.4 of SV LRM for more details
11. Explain about the virtual task and methods .
Ans:-
See http://www.testbench.in/CL_07_POLYMORPHISM.html
Answers to SystemVerilog Interview Questions - 5
(9)What is inheritance and polymorphism?
Please refer these links for more details on inheritance/polymorphism.
Ans:-
Queue
(16)How parallel case and full cases problems are avoided in SV ?
Ans:-
See Page 34/35 of http://www.systemverilog.org/pdf/SV_Symposium_2003.pdf
(22)What is the use of package?
Ans:-
In Verilog declaration of data/task/function within modules are specific to the module only. They can't be shared between two modules. Agreed, we can achieve the same via cross module referencing or by including the files, both of which are known to be not a great solution.
The package construct of SystemVerilog aims in solving the above issue. It allows having global data/task/function declaration which can be used across modules. It can contain module/class/function/task/constraints/covergroup and many more declarations (for complete list please refer section 18.2 of SV LRM 3.1a)
The content inside the package can be accessed using either scope resolution operator (::), or using import (with option of referencing particular or all content of the package).
package ABC;
// Some typedef
typedef enum {RED, GREEN, YELLOW} Color;
// Some function
void function do_nothing()
...
endfunction : do_nothing
// You can have many different declarations here
endpackage : ABC
// How to use them
import ABC::Color; // Just import Color
import ABC::*; // Import everything inside the package
(26)What is $root?
Ans:-
$root refers to the top level instance in SystemVerilog
package ABC; $root.A; // top level instance A $root.A.B.C; // item C within instance B within top level instance A
Answers to SystemVerilog Interview Questions - 4
(25)What is the difference between rand and randc?
Ans:-
rand - Random Variable, same value might come before all the the possible value have been returned. Analogous to throwing a dice.
randc - Random Cyclic Variable, same value doesn't get returned until all possible value have been returned. Analogous to picking of card from a deck of card without replacing. Resource intensive, use sparingly/judiciously
(24)How to call the task which is defined in parent object into derived class ?
Ans:-
super.task_name();
(21)What is the difference between always_combo and always@(*)?
Ans:-
From SystemVerilog LRM 3.1a:-
- always_comb get executed once at time 0, always @* waits till a change occurs on a signal in the inferred sensitivity list
- Statement within always_comb can't have blocking timing, event control, or fork-join statement. No such restriction of always @*
- Optionally EDA tool might perform additional checks to warn if the behavior within always_comb procedure doesn't represent combinatorial logic
- Variables on the left-hand side of assignments within an always_comb procedure, including variables
from the contents of a called function, shall not be written to by any other processes, whereas always @* permits multiple processes to write to the same variable. - always_comb is sensitive to changes within content of a function, whereas always @* is only sensitive to changes to the arguments to the function.
module dummy;
logic a, b, c, x, y;
// Example void function
function void my_xor;
input a; // b and c are hidden input here
x = a ^ b ^ c;
endfunction : my_xor
function void my_or;
input a; // b and c are hidden input here
y = a | b | c;
endfunction : my_xor
always_comb // equivalent to always(a,b,c)
my_xor(a); // Hidden inputs are also added to sensitivity list
always @* // equivalent to always(a)
my_or(a); // b and c are not added to sensitivity list
endmodule
(20)List the predefined randomization methods.
Ans:-
- randomize
- pre_randomize
- post_randomize
Ans:-
Scope randomization ins SystemVerilog allows assignment of unconstrained or constrained random value to the variable within current scope
module MyModule;
integer var, MIN;
initial begin
MIN = 50;
for ( int i = 0;i<10 ;i++) begin
if( randomize(var) with { var < 100 ; var > MIN ;})
$display(" Randomization sucsessfull : var = %0d Min = %0d",var,MIN);
else
$display("Randomization failed");
end
$finish;
end
endmodule
Answers to SystemVerilog Interview Questions - 3
(88)How to check weather a handles is holding object or not ?
Ans:-
It is basically checking if the object is initialized or not. In SystemVerilog all uninitialized object handles have a special value of null, and therefore whether it is holding an object or not can be found out by comparing the object handle to null. So the code will look like:-
usb_packet My_usb_packet;
...
if(My_usb_packet == null) begin
// This loop will get exited if the handle is not holding any object
....
end else begin
// Hurray ... the handle is holding an object
...
end
(87)What is the difference between initial block and final block?
Ans:-
There are many difference between initial and final block. I am listing the few differences that is coming to mind now.
- The most obvious one : Initial blocks get executed at the beginning of the simulation, final block at the end of simulation
- Final block has to be executed in zero time, which implies it can't have any delay, wait, or non-blocking assignments. Initial block doesn't have any such restrictions of execution in zero time (and can have delay, wait and non-blocking statements)
final begin
$display("Simulation Passed");
$display("Final value of xyz = %h",xyz);
$display("Bye :: So long, and Thanks for all the fishes");
end
(69)What is the difference between bits and logic?
Ans:-
bits is 2-valued (1/0) and logic is 4-valued (0/1/x/z)
(65)What is tagged union ?
Ans:-
An union is used to stored multiple different kind/size of data in the same storage location.
typedef union{
bit [31:0] a;
int b;
} data_u;
Now here XYZ union can contain either bit [31:0] data or an int data. It can be written with a bit [31:0] data and read-back with a int data. There is no type-checking done.
In the case where we want to enforce that the read-back data-type is same as the written data-type we can use tagged union which is declared using the qualifier tagged. Whenever an union is defined as tagged, it stores the tag information along with the value (in expense of few extra bits). The tag and values can only be updated together using a statically type-checked tagged union expression. The data member value can be read with a type that is consistent with current tag value, making it impossible to write one type and read another type of value in tagged union. (the details of which can be found in section 3.10 and 7.15 of SV LRM 3.1a).
typedef union tagged{
bit [31:0] a;
int b;
} data_tagged_u;
// Tagged union expression
data_tagged_u data1 = tagged a 32'h0;
data_tagged_u data2 = tagged b 5;
// Reading back the value
int xyz = data2.b;
(56)What is the need of alias in SV?
Ans:-
The Verilog has one-way assign statement is a unidirectional assignment and can contain delay and strength change. To have bidirectional short-circuit connection SystemVerilog has added alias statement. An excellent usage example of alias can be found out at http://www.systemverilog.org/pdf/SV_Symposium_2003.pdf(Slide # 59)
Few minor updates
Two small updates from my blog.
- My blog has started getting attentions from Verification community. Recently my blog got added to blogroll of VMM martial art blog (http://www.vmmcentral.org/vmartialarts/). Seems people are finding my blog worth reading/visiting. My blog is feeling blessed :)
- With almost 4-5 hrs of effort I could make syntaxhighlighter work (with small minor hiccups). It took way too much time as compared to what I hoped for, but the end result of it is worth it. A sample o/p from syntax highlighter.
// Byte Pack
function int unsigned atm_cell::byte_pack(ref logic [7:0] bytes[],
input int unsigned offset,
input int kind);
// Make sure there is enough room in the array
if(bytes.size() < this.byte_size())
bytes = new [this.byte_size()] (bytes);
// Pack the bytes
bytes[0] = {gfc, vpi[7:4]};
bytes[1] = {vpi[3:0], vci[15:12]};
bytes[2] = {vci[11:4]};
bytes[3] = {vci[3:0], pt, clp};
bytes[4] = {hec};
for (int i=0; i < 48; i++)
bytes[i+5]=payload[i];
byte_pack = 53;
endfunction
// Byte Unpack
function int unsigned atm_cell::byte_unpack(const ref logic[7:0] bytes[],
input int unsigned offset,
input int len,
input int kind);
{gfc, vpi, vci, pt, clp, hec} = {bytes[0], bytes[1], bytes[2],
bytes[3], bytes[4]};
for (int i = 0; i != 48; ++i)
payload[i] = bytes[i+5];
return 53;
endfunction
All about fork-join of System Verilog
I have added histstat hit counter for my blog to have an idea about traffic/visitor/search engine trends. One interesting I am observing is that quite a few hit to my site is coming for fork/join interview questions in Google. Hence I thought, why not have a real useful post on fork/join{x} of SystemVerilog and its associated disable/wait command.
Fork-join statement has come from Verilog. It is used for forking out parallel processes in test bench. SV substantially improved fork/join construct to have much more controllability in process creation, destruction, and waiting for end of the process.
The basic syntax of fork join block looks like this:
fork
begin : First_thread
// Code for 1st thread
end
begin : Second_thread
// Code for 2nd thread
end
begin : Third thread
// Code for 3rd branch
end
...
join // Can be join_any, join_none in SV
There are 3 different kind of join keyword in SV, each specifying a different way of waiting for completion of the threads/process created by the fork.
- join : waits for completion of all of the threads
- join_any : waits for the completion of the 1st thread, then comes out of fork loop, but lets the other process/thread execute as usual
- join_none : doesn't wait for completion of any thread, just starts then and immediately exits fork loop.
Now, suppose you have exited the fork loop by join_none or join_any and after some steps, you want to kill all the threads spanned by the previous fork loop. SV has "disable fork" for the same.
Next interesting scenario: you have exited fork loop by join_none or join_any and after some steps, you want to kill just one thread (out of many). The solution, have named begin end block and call "disable
I have created a image to pictorially depict fork/join in SV. Hope that will help understand this in a much better way.
VMM shorthand macros
Those who have worked with VMM based verification environment must have encountered situation where you need to code the different essential functions of vmm_data class like copy, psdisplay, compare and so on. This task become very tedious/boring when the number of classes you need to code is substantial, each having lengthy list of data member. Not long back, to get rid of the monotonicity of the above task, I sat for a day and wrote a perl script to generate the complete vmm_data class with essential functions from a class template.
Well, my one day effort is fixing the same is not worth the effort, as VMM has in-built short-hand-macros to solve it. It's especially useful when you don't have much non-standard data type (which are not supported by VMM shorthand macro)
class sample_class extends vmm_data;
// Simple scalar types
rand bit [7:0] da;
rand bit [8:0] db [10];
rand bit dc [];
rand bit dd [int];
rand bit de [string];
...
‘vmm_data_member_begin(sample_class)
‘vmm_data_member_scalar(da, DO_ALL)
‘vmm_data_member_scalar_array(db, DO_ALL)
‘vmm_data_member_scalar_da(dc, DO_ALL)
‘vmm_data_member_scalar_aa_scalar(dd, DO_ALL)
‘vmm_data_member_scalar_aa_string(de, DO_ALL)
‘vmm_data_member_end(sample_class)
...
endclass : sample_class
Some salient features of VMM shorthand macros are :
- They can be used for {scalar, string, enums, vmm_data, handles} x {normal, array, dynamic array, associative array (scalar, and string type)} combination (Total 25 types)
- These shorthands are valid for classes derived from vmm_data, vmm_env, vmm_subenv, vmm_xactor, and vmm_scenario
- The function which will get implemented depends upon what class your class is being instantiated from.
- For unlucky data member which doesn't fall into these 25 category, you can specify the same using `vmm_data_member_user_defined macro
Explain the difference between data types logic and reg and wire
Ans:-
To answer this I am not assuming the reader knows the answer for the difference between wire and reg.
Wire:-
- Wires are used for connecting different elements
- They can be treated as a physical wire
- They can be read or assigned
- No values get stored in them
- They need to be driven by either continuous assign statement or from a port of a module
- Contrary to their name, regs doesn't necessarily corresponds to physical registers
- They represents data storage elements in Verilog/SystemVerilog
- They retain their value till next value is assigned to them (not through assign statement)
- They can be synthesized to FF, latch or combinational circuit (They might not be synthesizable !!!)
Logic:-
- As we have seen, reg data type is bit mis-leading in Verilog. SystemVerilog's logic data type addition is to remove the above confusion. The idea behind having a new data type called logic which at least doesn't give an impression that it is hardware synthesizable
- Logic data type doesn't permit multiple driver. It has a last assignment wins behavior in case of multiple assignment (which implies it has no hardware equivalence). Reg/Wire data type give X if multiple driver try to drive them with different value. Logic data type simply assign the last assignment value.
- The next difference between reg/wire and logic is that logic can be both driven by assign block, output of a port and inside a procedural block like this
logic a;
assign a = b ^ c; // wire style
always (c or d) a = c + d; // reg style
MyModule module(.out(a), .in(xyz)); // wire style
Reference:-
SystemVerilog OOP links
Here are some nice OOP links on SystemVerilog OOP which can be used as a good starting point/reference.
- Object Oriented Programming for Hardware Verification
- Improve Your SystemVerilog OOP Skills by Learning Principles and Patterns
- SystemVerilog OOP OVM Feature SummarySystemVerilog OOP Ovm Features SummaryView more presentations from Amal Khailtash.
- Enhancing SystemVerilog with AOP Concepts (On how to mimic AOP features in OOP, good for guyz coming from e background)
- Testbench.in OOP Tutorial
Answers to SystemVerilog Interview Questions - 2
(86) What is the use of "extern"?
(66)What is "scope resolution operator"?
Ans:-
extern keyword allows out-of-body method declaration in classes. Scope resolution operator ( :: ) links method declaration to class declaration.
class XYZ;
// SayHello() will be declared outside the body
// of the class
extern void task SayHello();
endclass : XYZ
void task XYZ :: SayHello();
$Message("Hello !!!\n");
endtask : SayHello
(76) What is layered architecture ?
Ans:-
In SystemVerilog based constrained random verification environment, the test environment is divided into multiple layered as shown in the figure. It allows verification component re-use across verification projects.
(71)What is the difference between $rose and posedge?
Ans:-
posedge return an event, whereas $rose returns a Boolean value. Therefore they are not interchangeable.
(64)What is "this"?
Ans:-
"this" pointer refers to current instance.
(38)Write a clock generator without using always block.
Ans:-
initial begin
clk <= '0;
forever #(CYCLE/2) clk = ~clk
end
(35)How to implement always block logic in program block ?
Ans:-
Use of forever begin end. If it is a complex always block statement like always (@ posedge clk or negedge reset_)
always @(posedge clk or negedge reset_) begin
if(!reset_) begin
data <= '0;
end else begin
data <= data_next;
end
end
// Using forever : slightly complex but doable
forever begin
fork
begin : reset_logic
@ (negedge reset_);
data <= '0;
end : reset_logic
begin : clk_logic
@ (posedge clk);
if(!reset_) data <= '0;
else data <= data_next;
end : clk_logic
join_any
disable fork
end
Answers to SystemVerilog Interview Questions - I
Posting answers to few System Verilog Questions (Please refer System Verilog Interview Questions for questions)
10> What is the need of virtual interface ?
Ans:-
An interface encapsulate a group of inter-related wires, along with their directions (via modports) and synchronization details (via clocking block). The major usage of interface is to simplify the connection between modules.
But Interface can't be instantiated inside program block, class (or similar non-module entity in SystemVerilog). But they needed to be driven from verification environment like class. To solve this issue virtual interface concept was introduced in SV.
Virtual interface is a data type (that implies it can be instantiated in a class) which hold reference to an interface (that implies the class can drive the interface using the virtual interface). It provides a mechanism for separating abstract models and test programs from the actual signals that make up the design. Another big advantage of virtual interface is that class can dynamically connect to different physical interfaces in run time.
For more details please refer the following links
18> What is difference between $random() and $urandom()
Ans:-
- $random system function returns a 32-bit signed random number each time it is called
- $urandom system function returns a 32-bit unsigned random number each time it is called. (newly added in SV, not present in verilog)
47> How to randomize dynamic arrays of an object
Ans:-
class ABC; // Dynamic array rand bit [7:0] data []; // Constraints constraint cc { // Constraining size data.size inside {[1:10]}; // Constraining individual entry data[0] > 5; // All elements foreach(data[i]) if(i > 0) data[i] > data[i-1]; } endclass : ABC
Event Region, Scheduling Semantics in System Verilog
Let me start the post by asking one commonly asked interview question in verilog/system-verilog, that is what is the output of the following block
always @(posedge clk) begin
a = 0;
a <= 1;
$display(s);
end
To begin with let me be clear that this is not the correct way to code in verilog/SV. One shouldn't mix blocking and non-blocking assignment in the same begin-end block. But this question is asked to check the knowledge of scheduling semantics of verilog/SV.
Verilog scheduling semantics basically imply a four-level deep queue for the current simulation time:-
- Active Events (blocking assignment, RHS of NBA, continuous assignment, $display, ...)
- Inactive Events (#0 blocking assignment)
- Non-Blocking Assign Updates (LHS of NBA)
- Monitor Events ($monitor, $strobe).
System Verilog has added few more level queue for simulation, the details of which can be found in these 2 excellent link on scheduling semantics of SV.
The Hitchhiker series on Verification - From Mentor Graphics
It seems I am not the 1st one to have the Hichhiker series on SV-VMM. Back from 2007 time frame Mentor has a series of talk on System Verilog/AVM which is named as "The Hitchhiker Guide to XYZ". The good thing about these talks is that you don't need to register for watching these videos (almost all of the rest multimedia needs a registration for watching them). These are the links for your viewing and Learning:-
What is Factory Pattern
If you are working in System Verilog/VMM environment, it is high likely that you will be bombarded with word/expression from OOP world like "Factory Pattern", "Facade Pattern", "Observer Pattern" and so on. There is a finite possibility that you will seat down and start thinking what does those word mean and why they were used too frequently. Let me try to explain the idea/concept behind such word in the simplest way possible.
In SW engineering, a design pattern (or simply pattern) means a general repeatable solution to a commonly occurring problem. Most of these patterns have similarity to something or other in human society and hence they are known by that name.
Factory pattern as the name suggest, is aimed at solving the issue of creation of object. (Factory pattern is not the only pattern to deal with creation of objects, there are a bunch of more patterns for handling different kind of cases, and collectively they are known a creational patterns)
Let me give an example of case where we might need to use creational pattern and how to do so it in SV. Suppose you want to create a "Toy Factory" class which needs to create multiple types of toys (say toy aeroplane, toy tank, toy bus) depending upon the string input to it.
To create these different types of toys we need to have class defined for them. And there will be common method and data interface for these classes, hence it make sense to put all the common data member/task/functions in a class called toy class and then extend it.
class TOY;
// Common data memeber
string type;
// Common methods
virtual function string get_type();
endclass : TOY
class TOY_Tank extends TOY;
function new();
this.string = "Toy Tank";
endfunction : new
string function string get_type();
return this.string;
endfunction : get_type
endclass : TOY_Tank
class TOY_Bus extends TOY;
function new();
this.string = "Toy Bus";
endfunction : new
string function string get_type();
return this.string;
endfunction : get_type
endclass : TOY_Bus
Now we are done with the bothering about the objects to be created. The next problem that we need to solve is to write the toy factory class itself. For simplicity, let's consider the case where we will want to pass 1 to get an instance of tank class and 2 for getting an instance of bus class from the factory. Now the factory class will look like this.
class TOY_factory;
Toy my_toy
// Common methods
function toy get_toy(int type);
if(type == 1) this.my_toy = new TOY_Tank();
if(type == 2) this.my_toy = new TOY_Bus();
return this.my_toy;
endfunction : get_toy
endclass : TOY_factory
Note that we are using virtual function for bringing polymorphism in action and save us from having an individual instance of the toy type in the factory class.
Reference
- Factory Method Design Pattern from sourcemaking.com
- Factory Method Pattern from wikipedia
- Factory Pattern from JAVA design pattern
System Verilog Interview Questions
System Verilog Interview questions from http://www.edaboard.com/ftopic315416.html. I don't know answers to all of the questions, but will try to find out their answer from internet (thanks to the all powerful Google) and post the answers in this blog (one by one most likely). If you know answers to any of these then you are well come to share the same by commenting to this post.
- What is callback ?
- What is factory pattern ?
- Explain the difference between data types logic and reg and wire
- What is the need of clocking blocks ?
- What are the ways to avoid race condition between testbench and RTL using SystemVerilog?
- Explain Event regions in SV.
- What are the types of coverages available in SV ?
- What is OOPS?
- What is inheritance and polymorphism?
- What is the need of virtual interfaces ?
- Explain about the virtual task and methods .
- What is the use of the abstract class?
- What is the difference between mailbox and queue?
- What data structure you used to build scoreboard
- What are the advantages of linkedlist over the queue ?
- How parallel case and full cases problems are avoided in SV
- What is the difference between pure function and cordinary function ?
- What is the difference between $random and $urandom?
- What is scope randomization
- List the predefined randomization methods.
- What is the dfference between always_combo and always@(*)?
- What is the use of packagess?
- What is the use of $cast?
- How to call the task which is defined in parent object into derived class ?
- What is the difference between rand and randc?
- What is $root?
- What is $unit?
- What are bi-directional constraints?
- What is solve...before constraint ?
- Without using randomize method or rand,generate an array of unique values?
- Explain about pass by ref and pass by value?
- What is the difference between bit[7:0] sig_1; and byte sig_2;
- What is the difference between program block and module ?
- What is final block ?
- How to implement always block logic in program block ?
- What is the difference between fork/joins, fork/join_none fork/join_any ?
- What is the use of modports ?
- Write a clock generator without using always block.
- What is forward referencing and how to avoid this problem?
- What is circular dependency and how to avoid this problem ?
- What is cross coverage ?
- Describe the difference between Code Coverage and Functional Coverage Which is more important and Why we need them
- How to kill a process in fork/join?
- Difference between Associative array and Dynamic array ?
- Difference b/w Procedural and Concurrent Assertions?
- What are the advantages of SystemVerilog DPI?
- How to randomize dynamic arrays of objects?
- What is randsequence and what is its use?
- What is bin?
- Why always block is not allowed in program block?
- Which is best to use to model transaction? Struct or class ?
- How SV is more random stable then Verilog?
- Difference between assert and expect statements?
- How to add a new processs with out disturbing the random number generator state ?
- What is the need of alias in SV?
- What is the need to implement explicitly a copy() method inside a transaction , when we can simple assign one object to other ?
- How different is the implementation of a struct and union in SV.
- What is "this"?
- What is tagged union ?
- What is "scope resolution operator"?
- What is the difference between Verilog Parameterized Macros and SystemVerilog Parameterized Macros?
- What is the difference between
logic data_1; var logic data_2; wire logic data_3j; bit data_4; var bit data_5;
- What is the difference between bits and logic?
- Write a Statemechine in SV styles.
- What is the difference between $rose and posedge?
- What is advantage of program block over clockcblock w.r.t race condition?
- How to avoid the race condition between programblock ?
- What is the difference between assumes and assert?
- What is coverage driven verification?
- What is layered architecture ?
- What are the simulation phases in your verification environment?
- How to pick a element which is in queue from random index?
- What data structure is used to store data in your environment and why ?
- What is casting? Explain about the various types of casting available in SV.
- How to import all the items declared inside a package ?
- Explain how the timescale unit and precision are taken when a module does not have any timescalerdeclaration in RTL?
- What is streaming operator and what is its use?
- What are void functions ?
- How to make sure that a function argument passed has ref is not changed by the function?
- What is the use of "extern"?
- What is the difference between initial block and final block?
- How to check weather a handles is holding object or not ?
- How to disable multiple threads which are spawned by fork...join
What is this "System Verilog Callback"
Callback is one of the major confusing point for a System Verilog learner. Many people have asked the same question in many forums, but the answer doesn't seems to satisfy fully the quest of the person who has raised the querry. I too had the same issue, but I learned it slowly in a hard way. I am presenting here a way in which if I had an answer, I would have learned faster.
We can pass data member to any function. Now consider a case where you are passing a function (say func1) as a data member to another function (say func2) and you get what is called callback. The reason why it is called callback is that the function func2 now can call anywhere in its code function func1.
From wikipedia
In computer programming, a callback is executable code that is passed as an argument to other code. It allows a lower-level software layer to call a subroutine (or function) defined in a higher-level layer.
Note that SV doesn't give a straight-forward way of passing a function as argument for another function. But we can get the same result (almost we can say!) by using OOP. The idea is to describe all the functions (both func1 type and func2 type) in a base class (don't implement the funct2 kind of function and make them virtual for polymorphism), and then extend the class to a derived class where you implement the func2 type of function.
Example:-
class abc_transactor;
virtual task pre_send(); endtask
virtual task post_send(); endtask
task xyz();
// Some code here
this.pre_send();
// Some more code here
this.post_send();
// And some more code here
endtask : xyz
endclass : abc_transactor
class my_abc_transactor extend abc_transactor;
virtual task pre_send();
... // This function is implemented here
endtask
virtual task post_send();
... // This function is implemented here
endtask
endclass : my_abc_transactor
Now let me explain how it is going to work. The base class abc_transactor has 3 tasks, 2 of which are declared virtual and are not implemented. But they are being called from another task xyz() which is fully implemented. The unimplemented virtual task are called callback class.
The child class, which extends from the base class, implements the previous unimplemented tasks. It inherits the xyz() task from the base class and hence doesn't need to change it. By this we can inject executable code to a function without modifying it.
Now the next question is why is done. There are many reasons for it.
- The biggest advantage is that you can modify the behavior of task xyz() without modifying it in the base or child class. It is a big advantage as no one wants to fiddle with known good functioning code.
- Consider a case where you are writing a base class which is going to be used by multiple test environment, and for each test environment a known part of the code, or a known function/task is going to change. The natural choice is to implement those change-in-every-case functions/tasks as callback method and let the user extend your base class with specifying only that part of the code which need to be changed in his case.
Reference:-
System Verilog Gotchas - by Stuart Sutherland
In one of my last post I have added one of the System Verilog Gotcha paper. There are 2 more System Verilog Gotcha presentations (this time by Stuart Sutherland).
The compete presentation/papers of Stuart on System Verilog, Verification, Verilog can be viewed at http://www.sutherland-hdl.com/papers-by-sutherland.php
System Verilog LRM
System Verilog LRM, as the name suggest, is the definite reference manual for SV. Unlike other standard reference manual, which are too academic or boring to read, this one is a easy to use, easy to read and has large number of examples. The link of which can be easily got by a simple google search.
http://www.vhdl.org/sv/SystemVerilog_3.1a.pdf
There is another reference manual or standard for SV (IEEE 1800) which is pretty much same as the LRM, and you have to pay for downloading it (assuming your organization don't pay $$$ to IEEE for free access to its huge papers and standards)
Best sites to Learn System Verilog
There are large numbers of sites which have materials of system verilog, reading which you can learn it. But, there are few really good site, where system verilog has been described in a real nice way, and you have a smooth ride while learning SV. I personally learned from them quite a bit of system verilog from these sites.
- Testbench.in : System Verilog and VMM tutorial with a lots of example
- Asicguru.com : Another nice SV tutorial site
- Doulos SV Tutorial : Not that much extensive, but still good
- Another decent tutorial from Project-Veripage
- SV Tutorial from ASIC-World. It is not yet complete, but once it is complete, then it will be another great site to learn SV.
SV Tips/Tricks - Converting Strings to Enums
SystemVerilog enumerated data type has one major shortcoming namely the inability to covert string to enum data type, whereas the reverse is possible. But there are many cases when one find the need to do so. Thankfully JL Gray of verilab has created a sample class template which can be used for the same purpose. The link to the blog entry is
http://www.verilab.com/blog/2007/10/casting-strings-to-enums-in-systemverilog/
Enjoy maadi !!
System Verilog Basic Links
These days I am working on System Verilog/VMM (for those lucky one who don't know what these are, System Verilog is a Hardware Verification Language which is used for verifying complex multi-million gates digital designs, and VMM is a verification methodology for the same):-
Presentations:-
