The Ultimate Hitchhiker's Guide to Verification

Dumping ground of useful links/articles/tips/tricks on System Verilog/VMM/OVM as and when I stumble upon them and some of my views on it :)

Event Region, Scheduling Semantics in System Verilog

Let me start the post by asking one commonly asked interview question in verilog/system-verilog, that is what is the output of the following block


always @(posedge clk) begin
a = 0;
a <= 1;
$display(s);
end


To begin with let me be clear that this is not the correct way to code in verilog/SV. One shouldn't mix blocking and non-blocking assignment in the same begin-end block. But this question is asked to check the knowledge of scheduling semantics of verilog/SV.

Verilog scheduling semantics basically imply a four-level deep queue for the current simulation time:-
  1. Active Events (blocking assignment, RHS of NBA, continuous assignment, $display, ...)
  2. Inactive Events (#0 blocking assignment)
  3. Non-Blocking Assign Updates (LHS of NBA)
  4. Monitor Events ($monitor, $strobe).
Which implies, a=0 will be get printed in this example.

System Verilog has added few more level queue for simulation, the details of which can be found in these 2 excellent link on scheduling semantics of SV.

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