Let me start the post by asking one commonly asked interview question in verilog/system-verilog, that is what is the output of the following block
always @(posedge clk) begin
a = 0;
a <= 1;
To begin with let me be clear that this is not the correct way to code in verilog/SV. One shouldn't mix blocking and non-blocking assignment in the same begin-end block. But this question is asked to check the knowledge of scheduling semantics of verilog/SV.
Verilog scheduling semantics basically imply a four-level deep queue for the current simulation time:-
- Active Events (blocking assignment, RHS of NBA, continuous assignment, $display, ...)
- Inactive Events (#0 blocking assignment)
- Non-Blocking Assign Updates (LHS of NBA)
- Monitor Events ($monitor, $strobe).
System Verilog has added few more level queue for simulation, the details of which can be found in these 2 excellent link on scheduling semantics of SV.