To answer this I am not assuming the reader knows the answer for the difference between wire and reg.
- Wires are used for connecting different elements
- They can be treated as a physical wire
- They can be read or assigned
- No values get stored in them
- They need to be driven by either continuous assign statement or from a port of a module
- Contrary to their name, regs doesn't necessarily corresponds to physical registers
- They represents data storage elements in Verilog/SystemVerilog
- They retain their value till next value is assigned to them (not through assign statement)
- They can be synthesized to FF, latch or combinational circuit (They might not be synthesizable !!!)
- As we have seen, reg data type is bit mis-leading in Verilog. SystemVerilog's logic data type addition is to remove the above confusion. The idea behind having a new data type called logic which at least doesn't give an impression that it is hardware synthesizable
- Logic data type doesn't permit multiple driver. It has a last assignment wins behavior in case of multiple assignment (which implies it has no hardware equivalence). Reg/Wire data type give X if multiple driver try to drive them with different value. Logic data type simply assign the last assignment value.
- The next difference between reg/wire and logic is that logic can be both driven by assign block, output of a port and inside a procedural block like this
assign a = b ^ c; // wire style
always (c or d) a = c + d; // reg style
MyModule module(.out(a), .in(xyz)); // wire style