The Ultimate Hitchhiker's Guide to Verification

Dumping ground of useful links/articles/tips/tricks on System Verilog/VMM/OVM as and when I stumble upon them and some of my views on it :)

System Verilog Interview Questions

System Verilog Interview questions from http://www.edaboard.com/ftopic315416.html. I don't know answers to all of the questions, but will try to find out their answer from internet (thanks to the all powerful Google) and post the answers in this blog (one by one most likely). If you know answers to any of these then you are well come to share the same by commenting to this post.

  1. What is callback ?
  2. What is factory pattern ?
  3. Explain the difference between data types logic and reg and wire 
  4. What is the need of clocking blocks ?
  5. What are the ways to avoid race condition between testbench and RTL using SystemVerilog?
  6. Explain Event regions in SV.
  7. What are the types of coverages available in SV ? 
  8. What is OOPS?
  9. What is inheritance and polymorphism?
  10. What is the need of virtual interfaces ?
  11. Explain about the virtual task and methods .
  12. What is the use of the abstract class?
  13. What is the difference between mailbox and queue?
  14. What data structure you used to build scoreboard
  15. What are the advantages of linkedlist over the queue ?
  16. How parallel case and full cases problems are avoided in SV 
  17. What is the difference between pure function and cordinary function ?
  18. What is the difference between $random and $urandom?
  19. What is scope randomization 
  20. List the predefined randomization methods.
  21. What is the dfference between always_combo and always@(*)?
  22. What is the use of packagess?
  23. What is the use of $cast?
  24. How to call the task which is defined in parent object into derived class ?
  25. What is the difference between rand and randc?
  26. What is $root?
  27. What is $unit?
  28. What are bi-directional constraints?
  29. What is solve...before constraint ?
  30. Without using randomize method or rand,generate an array of unique values?
  31. Explain about pass by ref and pass by value?
  32. What is the difference between bit[7:0] sig_1; and byte sig_2;
  33. What is the difference between program block and module ?
  34. What is final block ?
  35. How to implement always block logic in program block ?
  36. What is the difference between fork/joins, fork/join_none fork/join_any ?
  37. What is the use of modports ? 
  38. Write a clock generator without using always block.
  39. What is forward referencing and how to avoid this problem?
  40. What is circular dependency and how to avoid this problem ?
  41. What is cross coverage ?
  42.  Describe the difference between Code Coverage and Functional Coverage Which is more important and Why we need them
  43. How to kill a process in fork/join?
  44. Difference between Associative array and Dynamic array ?
  45. Difference b/w Procedural and Concurrent Assertions?
  46. What are the advantages of SystemVerilog DPI?
  47. How to randomize dynamic arrays of objects?
  48. What is randsequence and what is its use?
  49. What is bin?
  50. Why always block is not allowed in program block?
  51. Which is best to use to model transaction? Struct or class ?
  52. How SV is more random stable then Verilog?
  53. Difference between assert and expect statements?
  54. How to add a new processs with out disturbing the random number generator state ?
  55. What is the need of alias in SV?
  56. What is the need to implement explicitly a copy() method inside a transaction , when we can simple assign one object to other ?
  57. How different is the implementation of a struct and union in SV.
  58. What is "this"?
  59. What is tagged union ?
  60. What is "scope resolution operator"?
  61. What is the difference between Verilog Parameterized Macros and SystemVerilog Parameterized Macros?
  62. What is the difference between



    logic data_1;
    var logic data_2;
    wire logic data_3j;
    bit data_4;
    var bit data_5;
    
  63. What is the difference between bits and logic?
  64. Write a Statemechine in SV styles.
  65. What is the difference between $rose and posedge?
  66. What is advantage of program block over clockcblock w.r.t race condition?
  67. How to avoid the race condition between programblock ?
  68. What is the difference between assumes and assert?
  69. What is coverage driven verification?
  70. What is layered architecture ?
  71. What are the simulation phases in your verification environment?
  72. How to pick a element which is in queue from random index?
  73. What data structure is used to store data in your environment and why ?
  74. What is casting? Explain about the various types of casting available in SV.
  75. How to import all the items declared inside a package ?
  76. Explain how the timescale unit and precision are taken when a module does not have any timescalerdeclaration in RTL?
  77. What is streaming operator and what is its use?
  78. What are void functions ?
  79. How to make sure that a function argument passed has ref is not changed by the function?
  80. What is the use of "extern"?
  81. What is the difference between initial block and final block?
  82. How to check weather a handles is holding object or not ?
  83. How to disable multiple threads which are spawned by fork...join

4 comments:

JK January 27, 2011 at 9:13 AM  

79. How to make sure that a function argument passed has ref is not changed by the function?

By using “const ref” type. With this, the compiler checks that your routine does not modify the array.
Eg:
function void print_sum (const ref int a[]);
int sum = 0;
for (int i=0; i<a.size; i++) begin
sum += a[i];
$display("The sum of the arrays is ", sum);
endfunction

JK January 27, 2011 at 9:14 AM  

76. Explain how the timescale unit and precision are taken when a module does not have any timescale declaration in RTL?

If a timeunit is not specified in the module, program, package, or interface definition, then the time unit shall be determined using the following rules of precedence:
a) If the module or interface definition is nested, then the time unit shall be inherited from the enclosing module or interface (programs and packages cannot be nested).
b) Else, if a ‘timescale directive has been previously specified (within the compilation unit), then the time unit shall be set to the units of the last ‘timescale directive.
c) Else, if the compilation-unit scope specifies a time unit (outside all other declarations), then the time unit shall be set to the time units of the compilation unit.
d) Else, the default time unit shall be used.

JK January 27, 2011 at 9:15 AM  

77. What is streaming operator and what is its use?

The streaming operators (pack/unpack) can be used to translate to and from a series of discrete variables, such as a set of class properties, and a stream of physical-level values. The streaming operators perform packing of bit-stream types into a sequence of bits in a user-specified order (OR) unpack a stream of bits into one or more variables. The stream operator determines the order in which data are streamed: >> causes data to be streamed in left-to-right order, while << causes data to be streamed in right-to-left order.

JK January 27, 2011 at 9:20 AM  

71. What are the simulation phases in your verification environment?

Prepone (sample) : Sampling signals before design activity. For testbench input.
Active (design) : Simulation of design code in modules
Observed (assertions) : Evaluation of System Verilog Assertions
Reactive(testbench) : Execution of testbench code in programs

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