The Ultimate Hitchhiker's Guide to Verification

Dumping ground of useful links/articles/tips/tricks on System Verilog/VMM/OVM as and when I stumble upon them and some of my views on it :)

Answers to SystemVerilog Interview Questions - 5

(9)What is inheritance and polymorphism?
 Please refer these links for more details on inheritance/polymorphism.

  2. SV OOP Links
(14)What data structure you used to build scoreboard?

(16)How parallel case and full cases problems are avoided in SV ?
See Page 34/35 of

(22)What is the use of package?
In Verilog declaration of data/task/function within modules are specific to the module only. They can't be shared between two modules. Agreed, we can achieve the same via cross module referencing or by including the files, both of which are known to be not a great solution.

The package construct of SystemVerilog aims in solving the above issue. It allows having global data/task/function declaration which can be used across modules. It can contain module/class/function/task/constraints/covergroup and many more declarations (for complete list please refer section 18.2 of SV LRM 3.1a)

The content inside the package can be accessed using either scope resolution operator (::), or using import (with option of referencing particular or all content of the package).

package ABC;
    // Some typedef
    typedef enum {RED, GREEN, YELLOW} Color;

    // Some function
    void function do_nothing()
    endfunction : do_nothing

    // You can have many different declarations here
endpackage : ABC

// How to use them
import ABC::Color;     // Just import Color
import ABC::*;         // Import everything inside the package

(26)What is $root?
$root refers to the top level instance in SystemVerilog

package ABC;
$root.A;       // top level instance A
$root.A.B.C;   // item C within instance B within top level instance A


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