The Ultimate Hitchhiker's Guide to Verification

Dumping ground of useful links/articles/tips/tricks on System Verilog/VMM/OVM as and when I stumble upon them and some of my views on it :)

Answers to SystemVerilog Interview Questions - 7

4. What is the need of clocking blocks ?
Clocking block in SystemVerilog are used for specifying the clock signal, timing, and synchronization requirements of various blocks. It separates the timing related information from structural, functional and procedural element of the TB. There are quite a few links on clocking block in the internet. These are links to learn about SV clocking blocks.

  1. AsicGuru :: To the point answer on the need of clocking block
  2. :: Clocking block  
  3. ProjectVeripage :: Clocking block 
  4. Doulos :: Clocking block 
  5. Asicworld :: Clocking block
  6. SystemVerilog Event Regions, Race Avoidance & Guidelines

 5. What are the ways to avoid race condition between testbench and RTL using SystemVerilog?
Short answer : -
  1. Program  block
  2. Clocking block
  3. Enforcement of design signals being driven in non-blocking fashion from program block
Long answer :-
Too long to describe here :). Please refer these doc/sections for more idea/info
  1. Section 16.4 of SV LRM
  4. VG discussion of the necessity of program block. 

7. What are the types of coverages available in SV ?
Using covergroup : variables, expression, and their cross
Using cover keyword : properties

12. What is the use of the abstract class?


music4soul March 20, 2012 at 10:41 PM  

In question What are the types of coverages available in SV? May be the quest or answer is incorrect.
The questions what are the types of coverage.
The answer talks about how functional coverage is done!

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