The Ultimate Hitchhiker's Guide to Verification

Dumping ground of useful links/articles/tips/tricks on System Verilog/VMM/OVM as and when I stumble upon them and some of my views on it :)

Have you ever heard of a programming language called "Whitespace"?

The question of the day is "Have you ever heard of a programming language called Whitespace?". If the answer is no then please refer to wikipedia article on in. Quoting directly from wikipedia for the lazy ones who would rather like to stay at this page rather than visit the wikipedia site

Whitespace is an esoteric programming language developed by Edwin Brady and Chris Morris at the University of Durham (also developers of the Kaya programming language). It was released on 1 April 2003 (April Fool's Day). Its name is a reference to whitespace characters. Unlike most programming languages, which ignore or assign little meaning to most whitespace characters, the Whitespace interpreter ignores any non-whitespace characters. Only spaces, tabs and linefeeds have meaning.[1] An interesting consequence of this property is that a Whitespace program can easily be contained within the whitespace characters of a program written in another language, making the text a polyglot.[citation needed]

Next question that shall be naturally occurring to you, why am I posting a link of some arbit/useless language in a blog which is devoted to verification. To answer this, I shall begin by asking you to find out the error in this code. Assume x, y, z to be simple logic variable.

`define SWAP(__a, __b) \
    __a = __a ^ __b;   \
    __b = __a ^ __b;   \ 
    __a = __a ^ __b; 


Couldn't find any issue with it. Let me show the above example with white space character as [space].

`define SWAP(__a, __b) \
    __a = __a ^ __b;   \
    __b = __a ^ __b;   \[space]
    __a = __a ^ __b; 


Now the issue is the extra white space character after \ of the SWAP macro definition. VCS doesn't like it and give some weird error which doesn't even tell that the error is due to the white-space after the \. I checked SV LRM and as per my understanding of reading the relevant section, it seems to be a valid system verilog code.

It took me half a day of banging my head in front of my monitor to find out that the issue is this extra whitespace after \ in the macro.

I feel Synopsys folks should do one of the following to make sure that no one else waste his precious time in debugging such hard-to-debug not-so-obvious issue.
  1. Ignore whitespce after \ in multi-line macro definition OR
  2. In case when a whitespace is encountered after \ in a multi-line macro, give error specifying that a whitespace character is encountered after \
Anyone from Synopsys listening ???

What is Factory Pattern - v2.0

This post is a extended version of my original post on factory pattern which can be found at

If you are working in System Verilog/VMM environment, it is high likely that you will be bombarded with word/expression from OOP world like "Factory Pattern", "Facade Pattern", "Observer Pattern" and so on. There is a finite possibility that you will seat down and start thinking what does those word mean and why they were used too frequently. Let me try to explain the idea/concept behind such word in the simplest way possible.

In SW engineering, a design pattern (or simply pattern) means a general repeatable solution to a commonly occurring problem. Most of these patterns have similarity to something or other in human society and hence they are known by that name.

Factory pattern as the name suggest, is aimed at solving the issue of creation of object. (Factory pattern is not the only pattern to deal with creation of objects, there are a bunch of more patterns for handling different kind of cases, and collectively they are known a creational patterns)

Let me give an example of case where we might need to use creational pattern and how to do so it in SV. Suppose you want to create a "Toy Factory" class which needs to create multiple types of toys (say toy aeroplane, toy tank, toy bus) depending upon the string input to it.

To create these different types of toys we need to have class defined for them. And there will be common method and data interface for these classes, hence it make sense to put all the common data member/task/functions in a class called toy class and then extend it.

class TOY;
    // Common data memeber
    string toy_name;

    // Common methods
    virtual function string get_type();
endclass : TOY

class TOY_Tank extends TOY;
    function new();
        this.toy_name = "Toy Tank";
    endfunction : new

    string function string get_type();
        return this.toy_name;
    endfunction : get_type
endclass : TOY_Tank

class TOY_Bus extends TOY;
    function new();
        this.toy_name = "Toy Bus";
    endfunction : new

    string function string get_type();
        return this.toy_name;
    endfunction : get_type
endclass : TOY_Bus

Now we are done with the bothering about the objects to be created. The next problem that we need to solve is to write the toy factory class itself. For simplicity, let's consider the case where we will want to pass 1 to get an instance of tank class and 2 for getting an instance of bus class from the factory. Now the factory class will look like this.
class TOY_factory;
    Toy my_toy

    // Common methods
    function toy get_toy(string str);
        if(str == "Toy Tank") this.my_toy = new TOY_Tank();
        if(str == "Toy Bus")  this.my_toy = new TOY_Bus();
        return this.my_toy;
    endfunction : get_toy
endclass : TOY_factory

Note that we are using virtual function for bringing polymorphism in action and save us from having an individual instance of the toy type in the factory class.


Mike Mintz has added the following word of caution/note for this in the thread

The above link is very good. I would just like to add a word of caution. The factory pattern should be rather rare in your architecture. While the choice of where to put the "new" for a class is very important, most of the time (for big components) the answer is in the testbench. That's where all the drivers,generators,monitors, etc should be built.

Also the factory pattern is usually implemented as a function, not a class. When it's a class, you can get sloppy with the necessary parameters and you code is harder to follow.

I understand pretty well the warping of these cautions caused by the three letter methodologies and their misguided quest for generic components, so your usage may have to follow their guidelines. Just remember that (1) in the real world factory patterns are rare, and (2) you do not always have to do it the way the methodology says.

    SystemVerilog-201x listening campaign - Brad are you still listening !!!

    It seems recently the big guys in System Verilog (like Brad Pierce, just to give an idea of how big these guyz are) have decided to listen to people for possible improvement in System Verilog. The interested guy can check this page [] and give his/her "most likely" valuable comment and feel good about being a part of improving System Verilog to next level !!! (These kind of feel good are the only kind of feel good one can feel in these era of sub-prime induced recession, and similar economic artifacts) I have few idea/suggestion on improvement in SV to make it much more powerful/user friendly. I am listing them in the hope that someone might listen them and add them.

    1. The keyword “singleton” for defining a class as singleton object. It shall get rid of the need of some weird way of getting singleton class in SV

      singleton class  ABC;
    2. Unified verification methodology should be defined as a part of SV. There are way too many methodology now a days (like OVM, AVM, VMM and so on …). There should be one such standard methodology. It shall make life far easier for so many engineer.
    3.  SV macros are a very powerful tool for reducing the amount of coding effort. SV improved quite a bit on verilog macro, but still there is a quite a bit scope for improvement. `` is a very rudimentary operator. It can’t be used for adding prefix to the input of the macro. See the hack that we need to do for adding prefix at

      `define PREFIX(__prefix, __name) __prefix“__name
      `define COV2(__name) `PREFIX(cp_,__name) : coverpoint __name {bins b = {1}; }
      // should be something like
      `define COV2(__name) cp_[[__name]] : coverpoint __name {bins b = {1}; } 
    4. There is scope for adding macro programming ability to SV. It should have the ability of generating code during macro processing phase.

      `for(int i=0; i<12; i++) begin \
      bind module_1 module_2 bind_mod_[[i]] (.*); \
    5. Ability to get signal by passing the hierarchical reference to the signal like wire a = get_signal(;
    6. Option of crossing two cross coverage.

      A : coverpoint ...
      B : coverpoint ...
      C : coverpoint ...
      D : coverpoint ...
      X : cross A, B;
      Y : cross C, D;
      // Z : cross X, Y; <----- SV doesn't allows it. It should

    Free Timing Diagram Drawing tools

    Many a times we need to generate/draw timing diagrams for multitude purposes. While browsing web for the same I came across these free/easy-to-use timing diagram drawing utilities.

    1. Timing Diagram Font  -- Timing diagram can be generated in MS Word using this
    2. Timing Analyzer -- A tool for doing the same
      1. Timing Diagram from verilog - using the above tool and small snippet of verilog code, one can generate timing waveform from the design itself. One problem I see with it is that the code snippet doesn't use verilog macro for achieving the same. 
    3. Handy Timer - A simple and handy timing diagram editor
    4. Timing Editor - Another free waveform editor
    5. Draw Timing - Command line based waveform drawing SW which take a script as its input
      Please let me know if you know some better/free timing diagram drawing tools that doesn't cost $$$.

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      I am from Sambalpur, Orissa, India. Have done Btech and Mtech in ECE from IIT Kharagpur. Currently working as Lead Member Technical Staff at Mentor Graphics Noida

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