The Ultimate Hitchhiker's Guide to Verification

Dumping ground of useful links/articles/tips/tricks on System Verilog/VMM/OVM as and when I stumble upon them and some of my views on it :)

Have you ever heard of a programming language called "Whitespace"?

The question of the day is "Have you ever heard of a programming language called Whitespace?". If the answer is no then please refer to wikipedia article on in. Quoting directly from wikipedia for the lazy ones who would rather like to stay at this page rather than visit the wikipedia site

Whitespace is an esoteric programming language developed by Edwin Brady and Chris Morris at the University of Durham (also developers of the Kaya programming language). It was released on 1 April 2003 (April Fool's Day). Its name is a reference to whitespace characters. Unlike most programming languages, which ignore or assign little meaning to most whitespace characters, the Whitespace interpreter ignores any non-whitespace characters. Only spaces, tabs and linefeeds have meaning.[1] An interesting consequence of this property is that a Whitespace program can easily be contained within the whitespace characters of a program written in another language, making the text a polyglot.[citation needed]

Next question that shall be naturally occurring to you, why am I posting a link of some arbit/useless language in a blog which is devoted to verification. To answer this, I shall begin by asking you to find out the error in this code. Assume x, y, z to be simple logic variable.

`define SWAP(__a, __b) \
    __a = __a ^ __b;   \
    __b = __a ^ __b;   \ 
    __a = __a ^ __b; 


Couldn't find any issue with it. Let me show the above example with white space character as [space].

`define SWAP(__a, __b) \
    __a = __a ^ __b;   \
    __b = __a ^ __b;   \[space]
    __a = __a ^ __b; 


Now the issue is the extra white space character after \ of the SWAP macro definition. VCS doesn't like it and give some weird error which doesn't even tell that the error is due to the white-space after the \. I checked SV LRM and as per my understanding of reading the relevant section, it seems to be a valid system verilog code.

It took me half a day of banging my head in front of my monitor to find out that the issue is this extra whitespace after \ in the macro.

I feel Synopsys folks should do one of the following to make sure that no one else waste his precious time in debugging such hard-to-debug not-so-obvious issue.
  1. Ignore whitespce after \ in multi-line macro definition OR
  2. In case when a whitespace is encountered after \ in a multi-line macro, give error specifying that a whitespace character is encountered after \
Anyone from Synopsys listening ???


Anonymous March 31, 2010 at 8:33 AM  
This comment has been removed by a blog administrator.
Ein April 4, 2010 at 6:34 PM  

Thank you for your comments to my blog.

Your articles are very informative.
I'd like to introduce your blog to more Japanese.

Subash July 9, 2010 at 11:57 AM  

Hi Ein,
You are welcome to do so.

Amiri March 6, 2011 at 8:47 AM  

The requirement for the backslash to be the absolute last character on the line (without allowing whitespace) is actually a common requirement in any language that allows multi-line macros (C, Unix shell scripts, etc). I guess that either the people who wrote vcs are used to this practice and didn't think much of it, or maybe there is even a good reason for the strict requirement.

srikanth March 22, 2011 at 4:26 AM  

Even on the Cadence Tool(NC-Verilog) is giving some non-sense error

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