SystemVerilog-201x listening campaign - Brad are you still listening !!!

It seems recently the big guys in System Verilog (like Brad Pierce, just to give an idea of how big these guyz are) have decided to listen to people for possible improvement in System Verilog. The interested guy can check this page [http://bradpierce.wordpress.com/2009/12/14/systemverilog-201x-listening-campaign/] and give his/her "most likely" valuable comment and feel good about being a part of improving System Verilog to next level !!! (These kind of feel good are the only kind of feel good one can feel in these era of sub-prime induced recession, and similar economic artifacts) I have few idea/suggestion on improvement in SV to make it much more powerful/user friendly. I am listing them in the hope that someone might listen them and add them.

1. The keyword “singleton” for defining a class as singleton object. It shall get rid of the need of some weird way of getting singleton class in SV
   
   

   singleton class  ABC;
   …
   endclass 

2. Unified verification methodology should be defined as a part of SV. There are way too many methodology now a days (like OVM, AVM, VMM and so on …). There should be one such standard methodology. It shall make life far easier for so many engineer.
3.  SV macros are a very powerful tool for reducing the amount of coding effort. SV improved quite a bit on verilog macro, but still there is a quite a bit scope for improvement. `` is a very rudimentary operator. It can’t be used for adding prefix to the input of the macro. See the hack that we need to do for adding prefix at http://learn-systemverilog.blogspot.com/2009/09/system-verilog-define-macros-why-and.html
   
   

   `define PREFIX(__prefix, __name) __prefix“__name
   `define COV2(__name) `PREFIX(cp_,__name) : coverpoint __name {bins b = {1}; }
   // should be something like
   `define COV2(__name) cp_[[__name]] : coverpoint __name {bins b = {1}; } 

4. There is scope for adding macro programming ability to SV. It should have the ability of generating code during macro processing phase.
   
   

   `for(int i=0; i<12; i++) begin \
   bind module_1 module_2 bind_mod_[[i]] (.*); \
   end 

5. Ability to get signal by passing the hierarchical reference to the signal like wire a = get_signal(top.dut.abc.xyz);
   
6. Option of crossing two cross coverage.
   
   

   A : coverpoint ...
   B : coverpoint ...
   C : coverpoint ...
   D : coverpoint ...
   
   X : cross A, B;
   Y : cross C, D;
   
   // Z : cross X, Y; <----- SV doesn't allows it. It should