tag:blogger.com,1999:blog-9671775428656244652024-03-13T22:16:15.108-07:00The Ultimate Hitchhiker's Guide to VerificationDumping ground of useful links/articles/tips/tricks on System Verilog/VMM/OVM as and when I stumble upon them and some of my views on it :)Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.comBlogger49125tag:blogger.com,1999:blog-967177542865624465.post-46120953295866795762012-06-05T05:04:00.000-07:002012-06-05T05:04:18.411-07:00Verification Intent Description Language - Thinking out of box<div dir="ltr" style="text-align: left;" trbidi="on">
<div style="text-align: justify;">
I am working on UPF these days (SW side, not on verification side). UPF is not exactly a new language, but it is build upon TCL language. So one need a TCL interpreter in SW side to parse and analyze it.</div>
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<br /></div>
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The biggest roadblock/pain I see (with my 5-6 year experience in verification industry) is that there are N numbers of verification language/methodologies (SV, vera, eRM, OVM, VMM, UVM, and what not). But there is a single underlying philosophy/strategy behind almost all of these verification methodology. The difference lies in in which way the promoter of the verification methodology has written the base class for them. There will always be interface, a driver, a monitor, a transactor, channels, protocol packets in all of these methodology (The name might change from one methodology to another). </div>
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<br /></div>
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So a verification engineer has to learn a new methodology, translate his verification intent to the suitable class structure as specified by the verification methodology, compile the code along with the base class, and then run the simulation. I feel that the translation of verification intent in a "pre-defined" way so that it get conformed to a XYM standard is an extra effort, which should be get rid off.</div>
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<br /></div>
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Now consider the case where you have written your TB in OVM, and found that one of the essential verification component, that is freely available to is written in OVM. Agreed that you can you some converter class to bind these two with a great amount of pain; but the question is why not think of a way to get rid of the pain.</div>
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<br /></div>
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See the main page of <a href="http://www.testbench.in/">http://www.testbench.in/</a>. There are 5 easy labs, for verifying the same HW. </div>
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<br /></div>
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Here is what I think should be one way to get rid of SV/XMM, and make any verification environment compatible with each other.</div>
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<br /></div>
<div style="text-align: justify;">
What if we specify our verification intent in some UPF like fashion, and there is a tool which can convert it to OVM/UVM/AVM/eRM, or can compile it natively.</div>
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<br /></div>
<div style="text-align: justify;">
Now consider the code present at <a href="http://www.testbench.in/UL_04_PHASE_1_TOP.html">http://www.testbench.in/UL_04_PHASE_1_TOP.html</a></div>
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<br /></div>
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Why not have a language where the verification engineer can specify it as</div>
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<br /></div>
<div style="text-align: justify;">
create_interface mem_interface \</div>
<div style="text-align: justify;">
-setup_time 5ns \</div>
<div style="text-align: justify;">
-hold_time 3 ns \</div>
<div style="text-align: justify;">
-signal {{mem_date 7 0} {mem_addr 7 0} {mem_en} {mem_rd_wr} }</div>
<div style="text-align: justify;">
-clocking clocking_xyz</div>
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<br /></div>
<div style="text-align: justify;">
create_packet fcs_pkt \</div>
<div style="text-align: justify;">
-fields {{length byte} {da byte} {sa 127 0}}</div>
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<br /></div>
<div style="text-align: justify;">
add_constraint constraint_1 \</div>
<div style="text-align: justify;">
-packet fcs_pkt \</div>
<div style="text-align: justify;">
-condition { byte < 10} \</div>
<div style="text-align: justify;">
-condition { sa != 0 }</div>
<div style="text-align: justify;">
<br /></div>
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Now this is providing verification intent in a crisp/language/methodology independent manner. Tools can be written which can then convert these to required methodology, and make life easier for verification engineer.</div>
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<br /></div>
<div style="text-align: justify;">
knock, knock ... Is anyone leading major verification efforts listening !!!</div>
</div>Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com0tag:blogger.com,1999:blog-967177542865624465.post-91880217262442146652011-11-28T03:31:00.001-08:002011-11-28T03:32:16.632-08:00Slides from DVCon UK 2011<div dir="ltr" style="text-align: left;" trbidi="on">
<a href="http://www.testandverification.com/downloads/DVConference2011/">http://www.testandverification.com/downloads/DVConference2011/</a></div>Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com0tag:blogger.com,1999:blog-967177542865624465.post-71923754786786309532011-11-25T02:30:00.001-08:002011-11-25T02:37:09.906-08:00Pointer to UPF standard online<div dir="ltr" style="text-align: left;" trbidi="on">
UPF 1.0 standard<br />
<ul style="text-align: left;">
<li><h3 class="r">
<a class="l" href="http://www.google.co.in/url?sa=t&rct=j&q=upf%202.0&source=web&cd=7&ved=0CEwQFjAG&url=http%3A%2F%2Fwww.accellera.org%2Fapps%2Fgroup_public%2Fdownload.php%2F887%2Fupf.v1.0.pdf&ei=f27PTub0OcPhiAKB4bTaCw&usg=AFQjCNGT4T6PulY98NNhjJsgKlPbv9LLSw&sig2=Vdcsz56w3FGNOsjZ7bOeAw&cad=rja">Unified Power Format (<em>UPF</em>) Standard</a></h3>
</li>
</ul>
UPF 2.0 standard via scribd. Can be viewed online.<br />
<ul style="text-align: left;">
<li><a href="http://www.scribd.com/doc/59271855/1801-2009-v-2-0">http://www.scribd.com/doc/59271855/1801-2009-v-2-0</a></li>
</ul>
</div>Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com0tag:blogger.com,1999:blog-967177542865624465.post-30328488611233443232011-11-17T01:44:00.001-08:002011-11-17T01:46:55.595-08:00A nice blog on Power Aware Verification/UPF<div dir="ltr" style="text-align: left;" trbidi="on">
Today I came across a nice blog on UPF/Low Power. Sharing it<br />
<ul style="text-align: left;">
<li><a href="http://blogs.synopsys.com/magicbluesmoke/" target="_blank">Magic Blue Scope </a></li>
</ul>
<br /></div>Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com0tag:blogger.com,1999:blog-967177542865624465.post-55099144726775976912011-09-19T04:13:00.000-07:002011-09-19T04:14:58.796-07:00Mentor Graphics NOIDA is hiring.<div dir="ltr" style="text-align: left;" trbidi="on">
Please mail me your resume at subash.nayak@gmail.com if you want to apply to any of the below jobs.
<br />
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<a href="http://2.bp.blogspot.com/-W-tTaozh7PI/TncjqRSLOtI/AAAAAAAAOtk/0FC_w-GVx-8/s1600/image001.jpg" imageanchor="1"><img border="0" src="http://2.bp.blogspot.com/-W-tTaozh7PI/TncjqRSLOtI/AAAAAAAAOtk/0FC_w-GVx-8/s1600/image001.jpg" /></a></div>
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Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com0tag:blogger.com,1999:blog-967177542865624465.post-66185593954670138702011-09-14T05:01:00.000-07:002011-09-14T05:01:29.406-07:00One small update<div dir="ltr" style="text-align: left;" trbidi="on">
Hi all,<br />
<br />
To begin with let me thank all for visiting my blog. I have got many feedback on how people (few whom I know personally, and many I don't know) have used my blog for learning SV and preparing for job interviews. It feel good knowing that I have contributed something positively (a very little, I know :)) to the society via my blog. <br />
<br />
There is a small news to share with you all. Recently I have joined Mentor Graphics NOIDA as LMTS, where I am involved in tool development effort. So it is hardcore C++ coding/debug for me, and very little SystemVerilog/Verification. So from now on I am planning to blog on C/C++/SW development mostly, little less SV.<br />
<br />
Regards,<br />
-Subash<br />
<br /></div>
Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com2tag:blogger.com,1999:blog-967177542865624465.post-26038877887682702782011-06-22T07:19:00.001-07:002011-06-22T07:19:59.860-07:00Wavedrom : Web based Waveform editor<div dir="ltr" style="text-align: left;" trbidi="on"><a href="http://code.google.com/p/wavedrom/">http://code.google.com/p/wavedrom/</a><br />
<br />
</div>Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com0tag:blogger.com,1999:blog-967177542865624465.post-21472791782418963872011-05-17T23:01:00.000-07:002011-05-17T23:01:46.726-07:00Few nice articles on UVM<div dir="ltr" style="text-align: left;" trbidi="on"><ul style="text-align: left;"><li><a href="http://www.low-powerdesign.com/article_Cadence-UVM_082310.html">A Practical Guide to Adopting the Universal Verification Methodology—Part 1</a><br />
</li>
<li><a href="http://www.low-powerdesign.com/article_Cadence-UVM_083010.html">A Practical Guide to Adopting the Universal Verification Methodology—Part 2</a><br />
</li>
<li><a href="http://www.low-powerdesign.com/article_Cadence-UVM_101010.html">A Practical Guide to Adopting the Universal Verification Methodology—Part 3</a><br />
</li>
<li><a href="http://www.low-powerdesign.com/article_Cadence-UVM_101810.html">A Practical Guide to Adopting the Universal Verification Methodology—Part 4</a><br />
</li>
</ul></div>Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com0tag:blogger.com,1999:blog-967177542865624465.post-65193327593822930712011-05-10T22:20:00.000-07:002011-05-10T22:20:16.695-07:00Easier UVM for Functional Verification by Mainstream Users :: From Doulos<div dir="ltr" style="text-align: left;" trbidi="on"><a href="http://www.doulos.com/knowhow/sysverilog/uvm/easier_uvm_paper/">http://www.doulos.com/knowhow/sysverilog/uvm/easier_uvm_paper/</a></div>Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com0tag:blogger.com,1999:blog-967177542865624465.post-19058660877952012672011-05-04T01:03:00.000-07:002011-05-04T01:03:46.031-07:00How Do I Get Environment Variable into a String in SystemVerilog<div dir="ltr" style="text-align: left;" trbidi="on"> <br />
<div class="articleTitle">From Synopsys Solvnet, Needs to have Solvnet id, seems to be specific to VCS</div><div class="articleTitle"><ol style="text-align: left;"><li><a href="https://solvnet.synopsys.com/retrieve/032548.html?charid=techupdate&tuid=413">https://solvnet.synopsys.com/retrieve/032548.html?charid=techupdate&tuid=413 </a></li>
</ol></div><div class="articleTitle"><br />
</div><div class="articleTitle"><br />
</div><div class="articleTitle"><br />
</div></div>Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com0tag:blogger.com,1999:blog-967177542865624465.post-69826687566597852112010-12-02T21:11:00.000-08:002010-12-02T21:11:46.679-08:00Some interesting article on VerificationThese are some nice article on verification, that I stumbled upon. Hope it will be useful for the reader<br />
<ul><li><a href="http://www.testbench.in/SystemVerilog_2009_enhancements.html">What is new in SV 2009</a></li>
<li> <a href="http://www.testbench.in/colorfull_messages_from_systemverilog.html"><span class="question">PASS and FAIL Messages with Colors...!</span></a></li>
</ul>Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com0tag:blogger.com,1999:blog-967177542865624465.post-66702999375676325042010-11-26T03:25:00.000-08:002010-11-27T20:42:56.822-08:00Doing "cvs add" recursivelyThose who are still stuck with the age-old CVS due to some unfortunate reason (in the age of Perforce ...), they must have encountered situations when they want to add multiple files/folders recursively. This is one command I found via google search which will help in such situation<br />
.<br />
<blockquote><pre><code> find . -type d -print | grep -v CVS | xargs cvs add
find . -type f -print | grep -v CVS | xargs cvs add</code></pre></blockquote>Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com0tag:blogger.com,1999:blog-967177542865624465.post-75193801784453330612010-07-19T12:05:00.000-07:002010-07-19T12:05:56.765-07:00Writing SystemVerilog assertion for checking "setup/hold time violation" type of conditions<div class="separator" style="clear: both; text-align: center;"></div><a href="http://zone.ni.com/images/reference/en-XX/help/371599D-01/setup_hold_req.gif" imageanchor="1" style="clear: left; float: left; margin-bottom: 1em; margin-right: 1em;"><img border="0" height="152" src="http://zone.ni.com/images/reference/en-XX/help/371599D-01/setup_hold_req.gif" width="200" /></a>Recently, I gave couple of internal lectures on basic and advanced features of SystemVerilog assertion at the organization that I am working at. After that, quite a few colleague of mine have started asking questions on SVA. Amongst all, the most interesting assertion question is how to write assertion for checking "setup/hold time violation" type of scenarion. To understand these scenario, let's start with a very common example, which can be extended for many similar case.<br />
<br />
<b>Problem statement:</b><br />
<blockquote><blockquote>Write assertion for checking that the signal "data" is stable for tSetup time before positive edge of clock, and should be stable for tHold time after positive edge of clock. Here tSetup/tHold will be of static delay like 1ns, 30ps or so on. There are no extra inherent assumptions added with it (like clock period, its relationship with tSetup/tHold, or how fast the signal data can toggle.</blockquote></blockquote><div class="separator" style="clear: both; text-align: center;"></div>This is a standard problem, with not so easy solution of writing assertion for it<br />
<br />
In Verilog there is a way of checking it, which unfortunately is not an assertion, and hence can't be used with formal tools like Jasper. (via <a href="http://www.edaboard.co.uk/requesting-help-on-writing-sv-assertions-t442372.html">http://www.edaboard.co.uk/requesting-help-on-writing-sv-assertions-t442372.html</a><a href="http://www.edaboard.co.uk/requesting-help-on-writing-sv-assertions-t442372.html">http://www.edaboard.co.uk/requesting-help-on-writing-sv-assertions-t442372.html</a>)<br />
<br />
<pre class="brush:sv">module timing_checks (input clk, en);
specify
specparam clk_high_time = 5;
specparam clk_low_time = 5;
$setup(en, negedge clk, clk_high_time * 4 / 5);
$hold(negedge clk, en, clk_low_time * 4 / 5);
endspecify
endmodule
</pre><br />
Now let's proceed with assumption that we want to write an assertion for checking the same, we are not very much happy with $setup/$hold of Verilog. Here is the solution<br />
<br />
<pre class="brush:sv">module timing_checks_in_sv (input clk, data, ...);
...
event ev_data_delayed_toggled;
always @(data)
begin
fork
begin
# tSetup;
-> ev_data_delayed_toggled;
end
join_none
end
property setup_hold_time_checker;
time curr_time;
@(posedge clk) (1, curr_time = $time) |->
@(ev_data_delayed_toggled) (($time - curr_time) > (tSetup + tHold));
endproperty : setup_hold_time_checker
ASSERT_SETUP_HOLD: assert property setup_hold_time_checker;
endmodule
</pre><br />
In the always block, we are triggering an event called ev_data_delayed_toggled, after tSetup time every time data toggles. Now the "setup/hold time" problem statement can be written as after posedge of clock, ev_data_delayed_toggled shouldn't get triggered within tSetup+tHold time. Now the problem statement has come to a form SVA timing check, which is specified in via the property.<br />
<br />
There are many such not so intuitive, interesting use-case scenarios for SVA. Interested readers can have a look at the below link for some more interesting scenarios.<br />
<ul><li><a href="http://www.verilab.com/files/sva_gate_paper_dvcon2006.pdf">http://www.verilab.com/files/sva_gate_paper_dvcon2006.pdf </a></li>
</ul>Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com0tag:blogger.com,1999:blog-967177542865624465.post-4809611925207780302010-07-18T03:33:00.000-07:002010-07-19T08:20:55.515-07:00System Verilog Fine Grain Process Control - They are actually used in standard methodologiesThanks to 2 articles in one Japanese blog, and google translate, I got to know that fine grain process control are use sparingly (mostly for process kill) in OVM/VMM. I am just pasting the link of these article in the hope that interested reader shall go through them, do some more research and get himself enlightened with the usage of fine grain process control of systemverilog.<br />
<ul><li><a href="http://translate.googleusercontent.com/translate_c?hl=en&ie=UTF-8&sl=auto&tl=en&u=http://blogs.yahoo.co.jp/verification_engineer/59054470.html&prev=_t&rurl=translate.google.com&twu=1&usg=ALkJrhjOSZ0EoNcjjN0ZvudlDkX1QuY1Wg">http://translate.googleusercontent.com/translate_c?hl=en&ie=UTF-8&sl=auto&tl=en&u=http://blogs.yahoo.co.jp/verification_engineer/59054470.html&prev=_t&rurl=translate.google.com&twu=1&usg=ALkJrhjOSZ0EoNcjjN0ZvudlDkX1QuY1Wg </a></li>
<li><a href="http://translate.googleusercontent.com/translate_c?hl=en&ie=UTF-8&sl=auto&tl=en&u=http://blogs.yahoo.co.jp/verification_engineer/59140597.html&prev=_t&rurl=translate.google.com&twu=1&usg=ALkJrhiVWUuHJqX6cjrKz5eHYaK3f_L8pg">http://translate.googleusercontent.com/translate_c?hl=en&ie=UTF-8&sl=auto&tl=en&u=http://blogs.yahoo.co.jp/verification_engineer/59140597.html&prev=_t&rurl=translate.google.com&twu=1&usg=ALkJrhiVWUuHJqX6cjrKz5eHYaK3f_L8pg</a></li>
</ul>Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com0tag:blogger.com,1999:blog-967177542865624465.post-61678494603143812502010-07-09T11:09:00.000-07:002010-07-19T08:21:22.435-07:00Advanced SystemVerilog Process Control – Beyond fork-join_X<b></b><br />
<div style="text-align: justify;"><b>Abstract— All the Hardware Verification Languages (HVL) have an inherent requirement to have process control capabilities like creation, control and destruction of process. Although Verilog language has incorporated such capabilities like named blocks and fork-join statements, but SystemVerilog has further extended these properties of verilog with introduction of fork-join_X, disable fork and fine grain process control. ―Fine grain process control is the least understood and least used capability amongst all the SystemVerilog process control capabilities. The main reason behind the same is due to the fact that SV LRM[1] has very brief and concise description (about two pages) of fine grain process control. This paper aims in de-mystifying the above constructs and shows the use of fine grain process control for much more flexible processes creation, their control as well as destruction capabilities. It discusses how per-instance-based process control and decoupling of ―how and when can be done using SV fine grain process control</b></div><br />
<div style="text-align: justify;"><b>Index Terms—Fine grain process control, Inbuilt process class of SystemVerilog, Per-instance based process control, Decoupling of how and when of processes.</b></div><div style="text-align: justify;"><br />
</div><div style="text-align: justify;"><b><span style="font-size: large;">I. INTRODUCTION</span></b><br />
<div style="text-align: left;">Process control capabilities like creation, control and destruction of processes are inherent requirements of any Hardware Verification Language. Verilog has named block, fork-join construct for controlling process creation, control and destruction. Below example will show some of the capabilities of verilog process control.<b> </b></div></div><br />
<pre class="brush: sv;">always @(posedge req) begin
fork
begin : Label1
wait(a);
disable Label2;
end
begin : Label2
wait(b);
end
join
end
</pre><br />
<a href="http://2.bp.blogspot.com/_YoLjCsSgrqg/So7RmoZR-gI/AAAAAAAAKYc/VisQ8hbxlkI/s1600/moz-screenshot-2.png" imageanchor="1" style="clear: left; float: left; margin-bottom: 1em; margin-right: 1em;"><img border="0" height="235" src="http://2.bp.blogspot.com/_YoLjCsSgrqg/So7RmoZR-gI/AAAAAAAAKYc/VisQ8hbxlkI/s320/moz-screenshot-2.png" width="320" /></a>In the above mentioned code snippet, we are creating two threads named “Label1” and “Label2” at every posedge of req. In the thread “Label1”, as soon as signal “a” becomes HIGH, it kills the thread “Label2”.<br />
<br />
But, there are few limitations in Verilog’s process creation, control as well as destruction. The main limitation of verilog’s fork-join statement is that there is very less flexibility in terms of when it should get out of fork loop. In addition, disabling of named block is not a good way of killing a process.<br />
<br />
SystemVerilog solved the 1st limitation of verilog’s process control capabilities by adding new constructs like join_any, join_none, disable fork and wait fork. These constructs are widely used for controlling process creation/control/destruction.<br />
<br />
However these constructs have further few limitations for finer control of process. Using the above constructs, we cannot suspend/resume/kill only a specific single process. SystemVerilog has a feature called “Fine grain process control” using which we can have much finer control on creation/control/destruction of process.<br />
<br />
<span style="font-size: large;"><b>II. FINE GRAIN PROCESS CONTROL</b></span><br />
Fine grain process control is meant for having finer control on processes compared to the control one can get using fork/join_x constructs. This is done using SystemVerilog’s inbuilt class called ’process’. Let’s look at the various feature of the above class and how to use them for finer control of processes.<br />
<br />
<b>A. Handle Creation and status check</b><br />
To control any process/thread, we need to get the handle of the above thread using calling “process::self()” method of process class. Below code snippet will show how to do the same.<br />
<br />
<pre class="brush: sv;">task abc(…);
process P;
process::state Pstate;
…
fork
begin
P = process::self();
…
Pstate = P.status();
end
join_none
endtask : abc
</pre><br />
A process can be created for each always, initial block, and begin…end statement inside fork…join_X and dynamic processes. In addition, we can check the status of any process by calling status() method. A process can be in either of these 5 states (FINISHED, RUNNING, WAITING, SUSPENDED, KIL). “process::state” is a enumerated value and its content can be displayed using .name() method.<br />
<br />
<b>B. Process Suspension, Resumption, Await and Kill</b><br />
Any process can be suspended or resumed by calling suspend() and resume() task of process class. Similarly, the process can be terminated by calling kill() method. The await() method blocks till the process is terminated. SystemVerilog code snippet given in section “USE-CASE: FINER CONTROL OF PROCESS”.<br />
<br />
There can be few race conditions when a process is waiting for some event/variable change and we suspend the process. The question is on what condition the process shall resume its execution. These are simple rules to know when the process shall get unblocked from the waiting event[2]<br />
<ol><li>If the process is waiting for a delay like (#100 or #20ns) while going to suspend state, it will not count the time spent while in suspend state as the delay.</li>
<li>If the process is waiting for an event (@(SV_event)) while going for suspend state, and the event has occurred when the process is at suspend state, then the process will be unblocked, and will start executing from the next while after resuming.</li>
<li>If the process is waiting for variable change (@(SV_variable) or wait(SV_variable)) : Check for change of the variable is not performed when the process is suspended and hence any variable change happened during the time when the process is in suspended state shall not unblock the process if it is waiting for variable change and is put to suspend state</li>
</ol> <br />
<span style="font-size: large;"><b> III. USE-CASE: PER-INSTANCE BASED FINER CONTROL OF PROCESSES.</b></span><br />
Consider a scenario where we have created some N numbers of thread/process in one task. From another task, we want to suspend/resume/kill selected few tasks depending upon some other external conditions. Fine grain process control is extremely well suited for these kinds of tasks. Let see an example code snippet to understand how it can be done.<br />
<br />
<pre class="brush: sv;">class fine_grain_process_ctrl_example;
// Data members
process p[20];
…
task spawn_thread;
for(int i=0; i<20; i++)
begin
fork
begin
p[i] = process::self();
run_thread();
end
join_none
end
endtask: spawn_thread
task control_thread;
…
// condition met for suspending p[i]
p[i].suspend();
…
// condition met for resuming p[j]
p[j].resume();
…
// condition met for killing p[k]
p[k].kill();
…
// Wait for completion of p[l]
p[l].await();
endtask: control_thread
endclass: fine_grain_process_ctrl_example
</pre><br />
In the above code snippet, we have a class called fine_grain_process_ctrl, which has an array of process handles. In the task spawan_thread, where we are creating 20 parallel threads (by calling some external task run_thread()), we are also storing the handle of the process into the process array. Now in the task control_thread, we are controlling the suspension/resumption/termination of the above threads (which can be done in per-instance basis) depending upon some condition).<br />
<br />
There is another advantage of the above way of doing the process control. Here effectively, we are de-coupling what to do in the thread, and how to handle thread. This decoupling is very useful for code-reuse. The details of the above aspect are described in more detail in next section.<br />
<br />
<span style="font-size: large;"><b>IV. USE-CASE: DECOUPLING HOW AND WHEN</b></span><br />
<br />
<span style="font-size: large;"><b> </b></span><br />
<a href="http://3.bp.blogspot.com/_YoLjCsSgrqg/TDdkFtVOoEI/AAAAAAAAMSE/zEKzSk2CjIg/s1600/How_n_When.PNG" imageanchor="1" style="clear: left; float: left; margin-bottom: 1em; margin-right: 1em;"><img border="0" height="250" src="http://3.bp.blogspot.com/_YoLjCsSgrqg/TDdkFtVOoEI/AAAAAAAAMSE/zEKzSk2CjIg/s320/How_n_When.PNG" width="320" /></a>Consider a case where you have already written a transactor which sends packets according to your requirements. Now you need to change your code to make it work in the low-power-world where you need to stop sending packets whenever the system enters low-power state and resume sending packet once you are out of it. You have coded “HOW” to send your packet, and now you need to incorporate “WHEN” to send it, which itself can be far more complex that the simple “HOW”.<br />
<br />
You can directly go and modify the transactor code to incorporate “WHEN” aspect of the packet transmission. There are quite a few reasons why you would rather not touch the code and do the same in another way.<br />
<br />
Fine grain process control can be very nicely used in such scenario. You can have a handle of the process of sending packet. Now using this handle, we can stop/resume execution of the process (thereby stopping/resuming sending of packet) by calling suspend/resume method. We can have another piece of code where we can code the logic which will have the logic that shall control “WHEN” to send the packet.<br />
<br />
<b>REFERENCES</b><br />
[1] "IEEE Standard For SystemVerilog - Unified Hardware Design, Specification and Verification Language," IEEE Computer Society, IEEE, New York, NY, IEEE Std 1800-2009<br />
[2] Article on “Fine Grain Process Control” at Synopsys Solvenet<br />
<ol><li><a href="https://solvnet.synopsys.com/retrieve/025656.html">https://solvnet.synopsys.com/retrieve/025656.html</a></li>
<li><a href="https://solvnet.synopsys.com/retrieve/025657.html">https://solvnet.synopsys.com/retrieve/025657.html</a></li>
<li><a href="https://solvnet.synopsys.com/retrieve/025658.html">https://solvnet.synopsys.com/retrieve/025658.html</a></li>
</ol>Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com0tag:blogger.com,1999:blog-967177542865624465.post-74722325049708689622010-04-03T12:07:00.000-07:002010-07-19T08:21:46.439-07:00System Verilog Fine Grain Process Control - Beyond SV LRM - Part IThere is exactly 1 and 1/2 page long section on "Fine grain process control" is SV LRM (along with not so easy to follow example). No wonder I have not seen much people using this nice feature of System Verilog. Fortunately Synopsys SolvNet has 3 nice article on it. I am listing them for reference. Hope it shall be useful to the reader. (NOTE : accessing these articles requires solvnet login, which I was told, is not so easy to obtain unless your organization has a vcs license, the truthfulness of which I have not yet verified)<br />
<br />
<br />
<table border="0" cellpadding="0" cellspacing="0" style="border-collapse: collapse; width: 468px;"><col style="width: 48pt;" width="64"></col> <col style="width: 303pt;" width="404"></col> <tbody>
<tr height="20" style="height: 15pt;"> <td class="xl66" height="20" style="height: 15pt; width: 48pt;" width="64">SN</td> <td style="width: 303pt;" width="404">Article Title</td> </tr>
<tr height="20" style="height: 15pt;"> <td class="xl66" height="20" style="height: 15pt;">1</td> <td class="xl65"><a href="http://solvnet.synopsys.com/myretrieve.jsp?id=025656" target="_parent">Fine Grain Process Control: Handle Creation & Status Check</a></td> </tr>
<tr height="20" style="height: 15pt;"> <td class="xl66" height="20" style="height: 15pt;">2</td> <td><a href="http://solvnet.synopsys.com/myretrieve.jsp?id=025657" target="_parent"><span style="color: black; text-decoration: none;">Fine Grain Process Control: Process Await & Kill</span></a></td> </tr>
<tr height="20" style="height: 15pt;"> <td class="xl66" height="20" style="height: 15pt;">3</td> <td><a href="http://solvnet.synopsys.com/myretrieve.jsp?id=025658" target="_parent"><span style="color: black; text-decoration: none;">Fine Grain Process Control: Process Suspend & Resume</span></a></td> </tr>
</tbody></table>Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com0tag:blogger.com,1999:blog-967177542865624465.post-91257901356796836802010-03-29T07:17:00.000-07:002010-03-29T07:21:15.124-07:00Have you ever heard of a programming language called "Whitespace"?The question of the day is "Have you ever heard of a programming language called <b>Whitespace</b>?". If the answer is no then please refer to <a href="http://en.wikipedia.org/wiki/Whitespace_%28programming_language%29">wikipedia article</a> on in. Quoting directly from wikipedia for the lazy ones who would rather like to stay at this page rather than visit the wikipedia site<br />
<br />
<blockquote><b>Whitespace</b> is an <a href="http://en.wikipedia.org/wiki/Esoteric_programming_language" title="Esoteric programming language">esoteric programming language</a> developed by <a class="new" href="http://en.wikipedia.org/w/index.php?title=Edwin_Brady&action=edit&redlink=1" title="Edwin Brady (page does not exist)">Edwin Brady</a> and <a class="new" href="http://en.wikipedia.org/w/index.php?title=Chris_Morris_%28computer_scientist%29&action=edit&redlink=1" title="Chris Morris (computer scientist) (page does not exist)">Chris Morris</a> at the <a class="mw-redirect" href="http://en.wikipedia.org/wiki/University_of_Durham" title="University of Durham">University of Durham</a> (also developers of the <a href="http://en.wikipedia.org/wiki/Kaya_%28programming_language%29" title="Kaya (programming language)">Kaya</a> programming language). It was released on 1 April 2003 (<a class="mw-redirect" href="http://en.wikipedia.org/wiki/April_Fool%27s_Day" title="April Fool's Day">April Fool's Day</a>). Its name is a reference to <a class="mw-redirect" href="http://en.wikipedia.org/wiki/Whitespace_%28computer_science%29" title="Whitespace (computer science)">whitespace characters</a>. Unlike most programming languages, which ignore or assign little meaning to most whitespace characters, the Whitespace interpreter ignores any non-whitespace characters. Only <a class="mw-redirect" href="http://en.wikipedia.org/wiki/Space_character" title="Space character">spaces</a>, <a class="mw-redirect" href="http://en.wikipedia.org/wiki/Tab_character" title="Tab character">tabs</a> and <a class="mw-redirect" href="http://en.wikipedia.org/wiki/Linefeed" title="Linefeed">linefeeds</a> have meaning.<sup class="reference" id="cite_ref-whitespace_0-0"><a href="http://en.wikipedia.org/wiki/Whitespace_%28programming_language%29#cite_note-whitespace-0">[1]</a></sup> An interesting consequence of this property is that a Whitespace program can easily be contained within the whitespace characters of a program written in another language, making the text a <a href="http://en.wikipedia.org/wiki/Polyglot_%28computing%29" title="Polyglot (computing)">polyglot</a>.<sup class="Template-Fact" style="white-space: nowrap;" title="This claim needs references to reliable sources from February 2010">[<i><a href="http://en.wikipedia.org/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed">citation needed</a></i>]</sup></blockquote><br />
Next question that shall be naturally occurring to you, why am I posting a link of some arbit/useless language in a blog which is devoted to verification. To answer this, I shall begin by asking you to find out the error in this code. Assume x, y, z to be simple logic variable.<br />
<br />
<pre class="brush: sv;">`define SWAP(__a, __b) \
__a = __a ^ __b; \
__b = __a ^ __b; \
__a = __a ^ __b;
...
`SWAP(x,y)
`SWAP(y,z)
...
</pre><br />
Couldn't find any issue with it. Let me show the above example with white space character as [space].<br />
<br />
<pre class="brush: sv;">`define SWAP(__a, __b) \
__a = __a ^ __b; \
__b = __a ^ __b; \<span style="color: red;">[space]</span>
__a = __a ^ __b;
...
`SWAP(x,y)
`SWAP(y,z)
...</pre><br />
Now the issue is the extra white space character after \ of the SWAP macro definition. VCS doesn't like it and give some weird error which doesn't even tell that the error is due to the white-space after the \. I checked SV LRM and as per my understanding of reading the relevant section, it seems to be a valid system verilog code.<br />
<br />
It took me half a day of banging my head in front of my monitor to find out that the issue is this extra whitespace after \ in the macro.<br />
<br />
I feel Synopsys folks should do one of the following to make sure that no one else waste his precious time in debugging such hard-to-debug not-so-obvious issue.<br />
<ol><li>Ignore whitespce after \ in multi-line macro definition OR</li>
<li> In case when a whitespace is encountered after \ in a multi-line macro, give error specifying that a whitespace character is encountered after \</li>
</ol>Anyone from Synopsys listening ???Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com5tag:blogger.com,1999:blog-967177542865624465.post-83804898744266310982010-03-10T09:03:00.000-08:002010-07-19T08:23:18.823-07:00What is Factory Pattern - v2.0<a href="http://www.codeproject.com/KB/architecture/FactoryPattern/FactoryPattern.gif" onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}"><img alt="" border="0" src="http://www.codeproject.com/KB/architecture/FactoryPattern/FactoryPattern.gif" style="cursor: pointer; float: right; height: 428px; margin: 0pt 0pt 10px 10px; width: 383px;" /></a> This post is a extended version of my original post on factory pattern which can be found at <a href="http://learn-systemverilog.blogspot.com/2009/08/what-is-factory-pattern.html">http://learn-systemverilog.blogspot.com/2009/08/what-is-factory-pattern.html</a><br />
<br />
If you are working in System Verilog/VMM environment, it is high likely that you will be bombarded with word/expression from OOP world like "Factory Pattern", "Facade Pattern", "Observer Pattern" and so on. There is a finite possibility that you will seat down and start thinking what does those word mean and why they were used too frequently. Let me try to explain the idea/concept behind such word in the simplest way possible.<br />
<br />
In SW engineering, a design pattern (or simply pattern) means a general repeatable solution to a commonly occurring problem. Most of these patterns have similarity to something or other in human society and hence they are known by that name.<br />
<br />
Factory pattern as the name suggest, is aimed at solving the issue of creation of object. (Factory pattern is not the only pattern to deal with creation of objects, there are a bunch of more patterns for handling different kind of cases, and collectively they are known a creational patterns)<br />
<br />
Let me give an example of case where we might need to use creational pattern and how to do so it in SV. Suppose you want to create a "Toy Factory" class which needs to create multiple types of toys (say toy aeroplane, toy tank, toy bus) depending upon the string input to it.<br />
<br />
To create these different types of toys we need to have class defined for them. And there will be common method and data interface for these classes, hence it make sense to put all the common data member/task/functions in a class called toy class and then extend it.<br />
<br />
<pre class="brush: sv;">class TOY;
// Common data memeber
string toy_name;
// Common methods
virtual function string get_type();
endclass : TOY
class TOY_Tank extends TOY;
function new();
this.toy_name = "Toy Tank";
endfunction : new
string function string get_type();
return this.toy_name;
endfunction : get_type
endclass : TOY_Tank
class TOY_Bus extends TOY;
function new();
this.toy_name = "Toy Bus";
endfunction : new
string function string get_type();
return this.toy_name;
endfunction : get_type
endclass : TOY_Bus
</pre><br />
Now we are done with the bothering about the objects to be created. The next problem that we need to solve is to write the toy factory class itself. For simplicity, let's consider the case where we will want to pass 1 to get an instance of tank class and 2 for getting an instance of bus class from the factory. Now the factory class will look like this.<br />
<pre class="brush: sv;">class TOY_factory;
Toy my_toy
// Common methods
function toy get_toy(string str);
if(str == "Toy Tank") this.my_toy = new TOY_Tank();
if(str == "Toy Bus") this.my_toy = new TOY_Bus();
return this.my_toy;
endfunction : get_toy
endclass : TOY_factory</pre><br />
Note that we are using virtual function for bringing polymorphism in action and save us from having an individual instance of the toy type in the factory class.<br />
<br />
<b><u>Reference</u></b><br />
<ul><li><a href="http://sourcemaking.com/design_patterns/factory_method">Factory Method Design Pattern</a> from sourcemaking.com</li>
<li><a href="http://en.wikipedia.org/wiki/Factory_method_pattern">Factory Method Pattern</a> from wikipedia</li>
<li><a href="http://www.allappforum.com/java_design_patterns/factory_pattern.htm">Factory Pattern</a> from JAVA design pattern</li>
</ul><br />
<br />
<b><u>Note</u></b><br />
<a href="http://www.trusster.com/">Mike Mintz</a> has added the following word of caution/note for this in the thread <a href="http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=3763">http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=3763</a><br />
<br />
<blockquote><span class="postbody">The above link is very good. I would just like to add a word of caution. The factory pattern should be rather rare in your architecture. While the choice of where to put the "new" for a class is very important, most of the time (for big components) the answer is in the testbench. That's where all the drivers,generators,monitors, etc should be built. <br />
<br />
Also the factory pattern is usually implemented as a function, not a class. When it's a class, you can get sloppy with the necessary parameters and you code is harder to follow. <br />
<br />
I understand pretty well the warping of these cautions caused by the three letter methodologies and their misguided quest for generic components, so your usage may have to follow their guidelines. Just remember that (1) in the real world factory patterns are rare, and (2) you do not always have to do it the way the methodology says. <br />
</span></blockquote><br />
<ul></ul>Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com2tag:blogger.com,1999:blog-967177542865624465.post-53237322094402967012010-03-07T10:07:00.000-08:002010-03-08T05:27:04.633-08:00SystemVerilog-201x listening campaign - Brad are you still listening !!!It seems recently the big guys in System Verilog (like <a href="http://bradpierce.wordpress.com/">Brad Pierce</a>, just to give an idea of how big these guyz are) have decided to listen to people for possible improvement in System Verilog. The interested guy can check this page [<a href="http://bradpierce.wordpress.com/2009/12/14/systemverilog-201x-listening-campaign/">http://bradpierce.wordpress.com/2009/12/14/systemverilog-201x-listening-campaign/</a>] and give his/her "most likely" valuable comment and feel good about being a part of improving System Verilog to next level !!! (These kind of feel good are the only kind of feel good one can feel in these era of sub-prime induced recession, and similar economic artifacts) I have few idea/suggestion on improvement in SV to make it much more powerful/user friendly. I am listing them in the hope that someone might listen them and add them.<br />
<br />
<ol><li>The keyword “singleton” for defining a class as singleton object. It shall get rid of the need of some weird way of getting singleton class in SV<br />
<br />
<pre class="brush: sv;">singleton class ABC;
…
endclass </pre></li>
<li> Unified verification methodology should be defined as a part of SV. There are way too many methodology now a days (like OVM, AVM, VMM and so on …). There should be one such standard methodology. It shall make life far easier for so many engineer.</li>
<li> SV macros are a very powerful tool for reducing the amount of coding effort. SV improved quite a bit on verilog macro, but still there is a quite a bit scope for improvement. `` is a very rudimentary operator. It can’t be used for adding prefix to the input of the macro. See the hack that we need to do for adding prefix at <a href="http://learn-systemverilog.blogspot.com/2009/09/system-verilog-define-macros-why-and.html" rel="nofollow">http://learn-systemverilog.blogspot.com/2009/09/system-verilog-define-macros-why-and.html</a><br />
<br />
<pre class="brush: sv;">`define PREFIX(__prefix, __name) __prefix“__name
`define COV2(__name) `PREFIX(cp_,__name) : coverpoint __name {bins b = {1}; }
// should be something like
`define COV2(__name) cp_[[__name]] : coverpoint __name {bins b = {1}; } </pre></li>
<li> There is scope for adding macro programming ability to SV. It should have the ability of generating code during macro processing phase.<br />
<br />
<pre class="brush: sv;">`for(int i=0; i<12; i++) begin \
bind module_1 module_2 bind_mod_[[i]] (.*); \
end </pre></li>
<li> Ability to get signal by passing the hierarchical reference to the signal like wire a = get_signal(top.dut.abc.xyz);<br />
</li>
<li> Option of crossing two cross coverage.<br />
<br />
<pre class="brush: sv;">A : coverpoint ...
B : coverpoint ...
C : coverpoint ...
D : coverpoint ...
X : cross A, B;
Y : cross C, D;
// Z : cross X, Y; <----- SV doesn't allows it. It should
</pre></li>
</ol>Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com0tag:blogger.com,1999:blog-967177542865624465.post-644178939466669332010-03-06T22:32:00.000-08:002010-03-06T23:41:05.210-08:00Free Timing Diagram Drawing toolsMany a times we need to generate/draw timing diagrams for multitude purposes. While browsing web for the same I came across these free/easy-to-use timing diagram drawing utilities.<br />
<ol><li><a href="http://www.pcserviceselectronics.co.uk/fonts/index.php">Timing Diagram Font</a> -- Timing diagram can be generated in MS Word using this</li>
<li><a href="http://www.timing-diagrams.com/dokuwiki/doku.php">Timing Analyzer</a> -- A tool for doing the same </li>
<ol><li><a href="http://www.timing-diagrams.com/dokuwiki/doku.php?id=app_notes:verilog">Timing Diagram from verilog</a> - using the above tool and small snippet of verilog code, one can generate timing waveform from the design itself. One problem I see with it is that the code snippet doesn't use verilog macro for achieving the same. </li>
</ol><li><a href="http://www.edaboard.com/ftopic48568.html">Handy Timer</a> - A simple and handy timing diagram editor </li>
<li><a href="http://sourceforge.net/projects/timingeditor/files/">Timing Editor</a> - Another free waveform editor</li>
<li><a href="http://drawtiming.sourceforge.net/index.html">Draw Timing</a> - Command line based waveform drawing SW which take a script as its input</li>
<ol></ol></ol>Please let me know if you know some better/free timing diagram drawing tools that doesn't cost $$$.Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com2tag:blogger.com,1999:blog-967177542865624465.post-66371062095392843342009-11-28T04:54:00.000-08:002009-11-28T04:54:42.938-08:00Deep vs Shallow Copy in SystemVerilogThis is another interesting aspect of SV, which beginners usually get confused. This is an excellent blog post @ trusser on the same.<br />
<ul><li><a href="http://www.trusster.com/verification/deep-versus-shallow-copy/">Deep versus Shallow Copy</a><br />
</li>
</ul>Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com0tag:blogger.com,1999:blog-967177542865624465.post-3855675579403028682009-11-22T10:24:00.000-08:002009-11-28T04:49:48.920-08:00Some interesting ways to get a delayed version of signal in SVIn TB world, sometime you will need a signal which is N clock delayed version of another signal. You can do it by using 9 intermediate variables, or use these.<br />
<br />
<pre class="brush: sv;">// I want 10 clock delayed version of signal abc
always @(posedge clk) begin
abc_10_clk_delayed_1 <= $past(abc, 10); // This works in vcs
abc_10_clk_delayed_2 <= repeat(10) @(posedge clk) abc;
end
</pre>Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com0tag:blogger.com,1999:blog-967177542865624465.post-48254954743287619282009-09-19T11:04:00.000-07:002009-09-19T11:12:09.225-07:00System Verilog `define macros : Why and how to use them (and where not to use!!!)I most confess, I have become a very big fan of SystemVerilog `define macro for the amount of effort I save because of using it. The big advantage of using this is that you can concisely describe your intention in a more readable (and less SystemVerilog syntax) using macro. Another advantage is you need to change only at one place if you find out that you need to change the expression you have used in 100 of places. The 3rd reason is that it is widely used in industry. Some example worth quoting are<br />
<ol><li><a href="http://www.verilab.com/files/dac2005_mal_sva_cov_paper_a4.pdf">Using SystemVerilog Assertions for Functional Coverage</a></li>
<li><a href="http://www.eda.org/ovl/pages/pdfs/dvcon07_cerny.pdf">Using SystemVerilog Assertions for Creating Property-Based Checkers</a></li>
<li><a href="http://www.sunburst-design.com/papers/CummingsSNUG2009SJ_SVA_Bind.pdf">SystemVerilog Assertions Design Tricks and SVA Bind Files</a> <br />
</li>
<li><a href="http://www.intelligentdv.com/documents/doxygen/vmm-1.0.0/vmm__data__macros_8sv.html">VMM and especially VMM data macro </a></li>
</ol>Next question : Where shall I get the required info on how to use SystemVerilog `define macro<br />
Ans : Web (thanks to the all powerful demi-god of internet ... Google)<br />
<ol><li><a href="http://www.google.co.in/#hl=en&safe=off&q=Systemverilog+Macro">http://www.google.co.in/#hl=en&safe=off&q=Systemverilog+Macro</a> </li>
<li>System Verilog LRM 3.1a : Section : 25.2</li>
<li>Sandeep Vaniya's <a href="http://sandeep-vaniya.blogspot.com/2008/04/advanced-use-of-define-macro-in.html">Advanced Use of define macro in SystemVerilog</a> (not so advanced actually !!!)<br />
</li>
</ol>From reading these it might be apparent that define macro can be used for adding a postfix to the variable, but not prefix. I was thinking the same after reading the description (they don't have a single example of adding prefix to the variable via `define. Confused ?? Let me explain by giving a concrete example<br />
<br />
<pre class="brush: sv;">// Example macro for a coverage class
// Aim : want to get ABC_cp : coverpoint ABC {bins b = {1}; }
// by calling `COV(ABC)
`define COV(__name) __name``_cp : coverpoint __name {bins b = {1}; }
// Next
// What to do if I want cp_ABC in place of ABC_cp as for the above example
// NOTE : I can't use cp_``__name as cp_ is not an input to the macro
// Solution
// Use nested macros
`define PREFIX(__prefix, __name) __prefix``__name
`define COV2(__name) `PREFIX(cp_,__name) : coverpoint __name {bins b = {1}; }
</pre>Nested macro is not a new thing in SV. They are being extensively used in VMM data macro class. But no example of nested macro and achieving of addition pre_fix to variable name in `define macro is bit puzzling to me. I tried the above in vcs and seems to work perfectly fine.<br />
<br />
Next, where not to use `define (SV other better alternatives to `define these cases)<br />
<ol><li><a href="http://csg.csail.mit.edu/6.375/papers/cummings-paramdesign-hdlcon02.pdf">New Verilog-2001 Techniques for Creating Parameterized Models (or Down With `define and Death of a defparam!)</a>: Bit old but still usefull<br />
</li>
</ol>Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com3tag:blogger.com,1999:blog-967177542865624465.post-59585779850818296512009-09-14T09:53:00.000-07:002009-09-14T09:54:55.404-07:00Answers to SystemVerilog Interview Questions - 8<b>13. What is the difference between mailbox and queue?</b><br />
Ans:- <br />
Mailbox are FIFO queue, which allows only atomic operations. They can be bounded/unbounded. A bounded mailbox can suspend the thread (while writing if full, while reading if empty) via get/put task. Thats why mailbox is well suited for communication between threads.<br />
<br />
<b>24. What is the use of $cast?</b><br />
Ans:-<br />
Typecasting in SV can be done either via static casting (<size>', <type>', <signed unsigned="">') or dynamic casting via $cast task/function. $cast is very similar to dynamic_cast of C++. It checks whether the casting is possible or not in run-time and errors-out if casting is not possible.</signed></type></size><br />
<br />
<b>27. What is $unit?</b><br />
Ans:- <br />
Refer these 2 doc form more details<br />
<ol><li><a href="http://www.systemverilog.org/pdf/SystemVerilog_Overall_31A.pdf">http://www.systemverilog.org/pdf/SystemVerilog_Overall_31A.pdf</a> </li>
<li>SV LRM 3.1a :: Section 18.3</li>
</ol><br />
<b>28 .What are bi-directional constraints?</b><br />
Ans:-<br />
Constraints by-default in SystemVerilog are bi-directional. That implies that the constraint solver doesn't follow the sequence in which the constraints are specified. All the variables are looked simultaneously. Even the procedural looking constrains like if ... else ... and -> constrains, both if and else part are tried to solve concurrently. For example (a==0) -> (b==1) shall be solved as all the possible solution of (!(a==0) || (b==1)).<br />
<br />
<b>29. What is solve...before constraint ?</b><br />
Ans:- <br />
In the case where the user want to specify the order in which the constraints solver shall solve the constraints, the user can specify the order via solve before construct. i.e.<br />
<br />
<pre class="brush: sv;">...
constraint XYZ {
a inside {[0:100]|;
b < 20;
a + b > 30;
solve a before b;
}
</pre><br />
The solution of the constraint doesn't change with solve before construct. But the probability of choosing a particular solution change by it.<br />
<br />
<b>40. What is circular dependency and how to avoid this problem ?</b><br />
Ans:-<br />
Over specifying the solving order might result in circular dependency, for which there is no solution, and the constraint solver might give error/warning or no constraining. Example<br />
<br />
<pre class="brush: sv;">...
int x, y, z;
constraint XYZ {
solve x before y;
solve y before z;
solve z before x;
....
}
</pre>Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com0tag:blogger.com,1999:blog-967177542865624465.post-43822287859097257012009-09-09T11:22:00.000-07:002009-09-14T09:54:35.582-07:00Answers to SystemVerilog Interview Questions - 7<b>4. What is the need of clocking blocks ?</b><br />
Ans:- <br />
Clocking block in SystemVerilog are used for specifying the clock signal, timing, and synchronization requirements of various blocks. It separates the timing related information from structural, functional and procedural element of the TB. There are quite a few links on clocking block in the internet. These are links to learn about SV clocking blocks.<br />
<ol><li><a href="http://www.asicguru.com/system-verilog/tutorial/clocking-block/11/">AsicGuru :: To the point answer on the need of clocking block </a><br />
</li>
<li><a href="http://draft.blogger.com/goog_1252512183317">Testbench.in :: <span id="goog_1252512183305"></span></a><a href="http://draft.blogger.com/goog_1252512183317">Clocking <span id="goog_1252512183306"></span></a><a href="http://draft.blogger.com/goog_1252512183317">block </a><a href="http://www.testbench.in/IF_04_CLOCKING_BLOCK.html"> </a></li>
<li><a href="http://www.project-veripage.com/clocking_block_1.php">ProjectVeripage :: Clocking block</a> </li>
<li><a href="http://www.doulos.com/knowhow/sysverilog/tutorial/clocking/">Doulos :: Clocking block</a> </li>
<li><a href="http://www.asic-world.com/systemverilog/clocking1.html">Asicworld :: Clocking block</a></li>
<li><a href="http://www.sunburst-design.com/papers/CummingsSNUG2006Boston_SystemVerilog_Events.pdf">SystemVerilog Event Regions, Race Avoidance & Guidelines</a></li>
</ol><br />
<b> 5. What are the ways to avoid race condition between testbench and RTL using SystemVerilog?</b><br />
Ans:-<br />
Short answer : -<br />
<ol><li>Program block<br />
</li>
<li>Clocking block </li>
<li>Enforcement of design signals being driven in non-blocking fashion from program block</li>
</ol>Long answer :- <br />
Too long to describe here :). Please refer these doc/sections for more idea/info<br />
<ol><li>Section 16.4 of SV LRM</li>
<li><a href="http://www.testbench.in/SV_24_PROGRAM_BLOCK.html">http://www.testbench.in/SV_24_PROGRAM_BLOCK.html</a></li>
<li><a href="http://www.sunburst-design.com/papers/CummingsSNUG2006Boston_SystemVerilog_Events.pdf">http://www.sunburst-design.com/papers/CummingsSNUG2006Boston_SystemVerilog_Events.pdf</a> </li>
<li><a href="http://www.verificationguild.com/modules.php?name=Forums&file=viewtopic&t=1347&start=0">VG discussion of the necessity of program block.</a> </li>
</ol><br />
<b>7. What are the types of coverages available in SV ? </b><br />
Ans:-<br />
Using covergroup : variables, expression, and their cross<br />
Using cover keyword : properties<br />
<br />
<b>12. What is the use of the abstract class?</b><br />
Ans:-<br />
<ul><li><a href="http://www.testbench.in/CL_08_ABSTRACT_CLASSES.html">http://www.testbench.in/CL_08_ABSTRACT_CLASSES.html</a> </li>
</ul>Subashhttp://www.blogger.com/profile/03095917153942037871noreply@blogger.com1