(30)Without using randomize method or rand,generate an array of unique values?
... int UniqVal; foreach(UniqVal[i]) UniqVal[i] = i; UniqVal.shuffle(); ...
(32)What is the difference between byte and bit [7:0]?
byte is signed whereas bit [7:0] is unsigned.
(33)What is the difference between program block and module?
Program block is newly added in SystemVerilog. It serves these purposes
- It separates testbench from DUT
- It helps in ensuring that testbench doesn't have any race condition with DUT
- It provides an entry point for execution of testbench
- It provides syntactic context (via program ... endprogram) that specifies scheduling in the Reactive Region.
- Program blocks can't have always block inside them, modules can have.
- Program blocks can't contain UDP, modules, or other instance of program block inside them. Modules don't have any such restrictions.
- Inside a program block, program variable can only be assigned using blocking assignment and non-program variables can only be assigned using non-blocking assignments. No such restrictions on module
- Program blocks get executed in the re-active region of scheduling queue, module blocks get executed in the active region
- A program can call a task or function in modules or other programs. But a module can not call a task or function in a program.
- http://www.project-veripage.com/program_blocks_1.php and few more next/next !!!
- Section 16, SystemVerilog LRM 3.1a ... It's worth the effort reading line-by-line (and between the lines if you can :) ).
Modports are part of Interface. Modports are used for specifing the direction of the signals with respect to various modules the interface connects to.
... interface my_intf; wire x, y, z; modport master (input x, y, output z); modport slave (output x, y, input z); endinterface
Please refer section 19.4 of SV LRM for more details
11. Explain about the virtual task and methods .