The Ultimate Hitchhiker's Guide to Verification

Dumping ground of useful links/articles/tips/tricks on System Verilog/VMM/OVM as and when I stumble upon them and some of my views on it :)

Answers to SystemVerilog Interview Questions - 6

(30)Without using randomize method or rand,generate an array of unique values?

int UniqVal[10];
foreach(UniqVal[i]) UniqVal[i] = i;

(32)What is the difference between byte and bit [7:0]?
byte is signed whereas bit [7:0] is unsigned.

(33)What is the difference between program block and module?
Program block is newly added in SystemVerilog. It serves these purposes
  1. It separates testbench from DUT
  2. It helps in ensuring that testbench doesn't have any race condition with DUT
  3. It provides an entry point for execution of testbench
  4. It provides syntactic context (via program ... endprogram) that specifies scheduling in the Reactive Region.
Having said this the major difference between module and program blocks are
  1. Program blocks can't have always block inside them, modules can have.
  2. Program blocks can't contain UDP, modules, or other instance of program block inside them. Modules don't have any such restrictions.
  3. Inside a program block, program variable can only be assigned using blocking assignment and non-program variables can only be assigned using non-blocking assignments. No such restrictions on module
  4. Program blocks get executed in the re-active region of scheduling queue, module blocks get executed in the active region
  5. A program can call a task or function in modules or other programs. But a module can not call a task or function in a program.
More details:-
  2. and few more next/next !!!
  3. Section 16, SystemVerilog LRM 3.1a ... It's worth the effort reading line-by-line (and between the lines if you can :) ).
(37)What is the use of modports?
Modports are part of Interface. Modports are used for specifing the direction of the signals with respect to various modules the interface connects to.

interface my_intf;
    wire x, y, z;
    modport master (input x, y, output z);
    modport slave  (output x, y, input z);

Please refer section 19.4 of SV LRM for more details

11. Explain about the virtual task and methods .


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