The Ultimate Hitchhiker's Guide to Verification

Dumping ground of useful links/articles/tips/tricks on System Verilog/VMM/OVM as and when I stumble upon them and some of my views on it :)

Answers to SystemVerilog Interview Questions - 4

(25)What is the difference between rand and randc?

 Ans:-
rand - Random Variable, same value might come before all the the possible value have been returned. Analogous to throwing a dice.

randc - Random Cyclic Variable, same value doesn't get returned until all possible value have been returned. Analogous to picking of card from a deck of card without replacing. Resource intensive, use sparingly/judiciously
 
(24)How to call the task which is defined in parent object into derived class ?
Ans:-
super.task_name();

(21)What is the difference between always_combo and always@(*)?
 Ans:-
 From SystemVerilog LRM 3.1a:-

  1. always_comb get executed once at time 0, always @* waits till a change occurs on a signal in the inferred sensitivity list
  2. Statement within always_comb can't have blocking timing, event control, or fork-join statement. No such restriction of always @*
  3. Optionally EDA tool might perform additional checks to warn if the behavior within always_comb procedure doesn't represent combinatorial logic
  4. Variables on the left-hand side of assignments within an always_comb procedure, including variables
    from the contents of a called function, shall not be written to by any other processes, whereas always @* permits multiple processes to write to the same variable.
  5. always_comb is sensitive to changes within content of a function, whereas always @* is only sensitive to changes to the arguments to the function.
A small SystemVerilog code snippet to illustrate #5


module dummy;
    logic a, b, c, x, y;

    // Example void function
    function void my_xor;
        input a;           // b and c are hidden input here
        x = a ^ b ^ c;
    endfunction : my_xor

    function void my_or;
        input a;           // b and c are hidden input here
        y = a | b | c;
    endfunction : my_xor
    
    always_comb            // equivalent to always(a,b,c)
        my_xor(a);         // Hidden inputs are also added to sensitivity list

    always @*              // equivalent to always(a)
        my_or(a);          // b and c are not added to sensitivity list
endmodule

(20)List the predefined randomization methods.
  Ans:-
  1. randomize
  2. pre_randomize
  3. post_randomize
(19)What is scope randomization ?
  Ans:-
  Scope randomization ins SystemVerilog allows assignment of unconstrained or constrained random value to the variable within current scope

module MyModule;      
integer var, MIN;      

initial begin          
    MIN = 50;          
    for ( int i = 0;i<10 ;i++) begin              
        if( randomize(var) with { var < 100 ; var > MIN ;})  
            $display(" Randomization sucsessfull : var = %0d Min = %0d",var,MIN);   
        else                  
            $display("Randomization failed");
    end
          
    $finish;     
end
endmodule

0 comments:

Post a Comment

About Me

My photo
I am from Sambalpur, Orissa, India. Have done Btech and Mtech in ECE from IIT Kharagpur. Currently working as Lead Member Technical Staff at Mentor Graphics Noida

My Feedburner

Followers

Search This Blog

My Shelfari Bookshelf

Shelfari: Book reviews on your book blog

 

Traffic Summary