The Ultimate Hitchhiker's Guide to Verification

Dumping ground of useful links/articles/tips/tricks on System Verilog/VMM/OVM as and when I stumble upon them and some of my views on it :)

Answers to SystemVerilog Interview Questions - 2

(86) What is the use of "extern"?
(66)What is "scope resolution operator"?

Ans:-
extern keyword allows out-of-body method declaration in classes. Scope resolution operator ( :: ) links method declaration to class declaration.

class XYZ;
// SayHello() will be declared outside the body
// of the class
extern void task SayHello();
endclass : XYZ

void task XYZ :: SayHello();
$Message("Hello !!!\n");
endtask : SayHello




(76) What is layered architecture ?

Ans:-
In SystemVerilog based constrained random verification environment, the test environment is divided into multiple layered as shown in the figure. It allows verification component re-use across verification projects.

(71)What is the difference between $rose and posedge?

Ans:-
posedge return an event, whereas $rose returns a Boolean value. Therefore they are not interchangeable.

(64)What is "this"?

Ans:-
"this" pointer refers to current instance.

(38)Write a clock generator without using always block.

Ans:-
initial begin
clk <= '0;
forever #(CYCLE/2) clk = ~clk
end


(35)How to implement always block logic in program block ?

Ans:-

Use of forever begin end. If it is a complex always block statement like always (@ posedge clk or negedge reset_)

always @(posedge clk or negedge reset_) begin
if(!reset_) begin
data <= '0;
end else begin
data <= data_next;
end
end

// Using forever : slightly complex but doable
forever begin
fork
begin : reset_logic
@ (negedge reset_);
data <= '0;
end : reset_logic
begin : clk_logic
@ (posedge clk);
if(!reset_) data <= '0;
else data <= data_next;
end : clk_logic
join_any
disable fork
end

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