Answers to SystemVerilog Interview Questions - I

Posting answers to few System Verilog Questions (Please refer System Verilog Interview Questions for questions)

10> What is the need of virtual interface ?
Ans:-
An interface encapsulate a group of inter-related wires, along with their directions (via modports) and synchronization details (via clocking block). The major usage of interface is to simplify the connection between modules.

But Interface can't be instantiated inside program block, class (or similar non-module entity in SystemVerilog). But they needed to be driven from verification environment like class. To solve this issue virtual interface concept was introduced in SV.

Virtual interface is a data type (that implies it can be instantiated in a class) which hold reference to an interface (that implies the class can drive the interface using the virtual interface). It provides a mechanism for separating abstract models and test programs from the actual signals that make up the design. Another big advantage of virtual interface is that class can dynamically connect to different physical interfaces in run time.

For more details please refer the following links

• Testbench.in Interface tutorial
• Asicworld.com Interface tutorial

18> What is difference between $random() and $urandom()
Ans:-

1. $random system function returns a 32-bit signed random number each time it is called
2. $urandom system function returns a 32-bit unsigned random number each time it is called. (newly added in SV, not present in verilog)
   

47> How to randomize dynamic arrays of an object
Ans:-

class ABC;
// Dynamic array
rand bit [7:0] data [];

// Constraints
constraint cc {
// Constraining size
data.size inside {[1:10]};

// Constraining individual entry
data[0] > 5;

// All elements
foreach(data[i])
if(i > 0)
data[i] > data[i-1];
}
endclass : ABC