Answers to SystemVerilog Interview Questions - 3

(88)How to check weather a handles is holding object or not ?
Ans:-
It is basically checking if the object is initialized or not. In SystemVerilog all uninitialized object handles have a special value of null, and therefore whether it is holding an object or not can be found out by comparing the object handle to null. So the code will look like:-

usb_packet My_usb_packet; 
...
if(My_usb_packet == null) begin
    // This loop will get exited if the handle is not holding any object
    ....
end else begin
    // Hurray ... the handle is holding an object
    ...
end

(87)What is the difference between initial block and final block?
Ans:-
There are many difference between initial and final block. I am listing the few differences that is coming to mind now.

1. The most obvious one : Initial blocks get executed at the beginning of the simulation, final block at the end of simulation
2. Final block has to be executed in zero time, which implies it can't have any delay, wait, or non-blocking assignments. Initial block doesn't have any such restrictions of execution in zero time (and can have delay, wait and non-blocking statements)

Final block can be used to display statistical/genaral information regarding the status of the execution like this:-

final begin
    $display("Simulation Passed");
    $display("Final value of xyz = %h",xyz);
    $display("Bye :: So long, and Thanks for all the fishes");
end

(69)What is the difference between bits and logic?
Ans:-
bits is 2-valued (1/0) and logic is 4-valued (0/1/x/z)

(65)What is tagged union ?
Ans:-
An union is used to stored multiple different kind/size of data in the same storage location.

typedef union{
    bit [31:0]  a;
    int         b;
} data_u;

Now here XYZ union can contain either bit [31:0] data or an int data. It can be written with a bit [31:0] data and read-back with a int data. There is no type-checking done.

In the case where we want to enforce that the read-back data-type is same as the written data-type we can use tagged union which is declared using the qualifier tagged. Whenever an union is defined as tagged, it stores the tag information along with the value (in expense of few extra bits). The tag and values can only be updated together using a statically type-checked tagged union expression. The data member value can be read with a type that is consistent with current tag value, making it impossible to write one type and read another type of value in tagged union. (the details of which can be found in section 3.10 and 7.15 of SV LRM 3.1a).

typedef union tagged{
    bit [31:0]  a;
    int         b;
} data_tagged_u;

// Tagged union expression
data_tagged_u data1 = tagged a 32'h0;
data_tagged_u data2 = tagged b 5;

// Reading back the value
int xyz = data2.b;

(56)What is the need of alias in SV?
Ans:-
The Verilog has one-way assign statement is a unidirectional assignment and can contain delay and strength change. To have bidirectional short-circuit connection SystemVerilog has added alias statement. An excellent usage example of alias can be found out at http://www.systemverilog.org/pdf/SV_Symposium_2003.pdf(Slide # 59)