The Ultimate Hitchhiker's Guide to Verification

Dumping ground of useful links/articles/tips/tricks on System Verilog/VMM/OVM as and when I stumble upon them and some of my views on it :)

Some interesting ways to get a delayed version of signal in SV

In TB world, sometime you will need a signal which is N clock delayed version of another signal. You can do it by using 9 intermediate variables, or use these.

// I want 10 clock delayed version of signal abc
always @(posedge clk) begin
    abc_10_clk_delayed_1 <= $past(abc, 10); // This works in vcs
    abc_10_clk_delayed_2 <= repeat(10) @(posedge clk) abc;


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