The Ultimate Hitchhiker's Guide to Verification

Dumping ground of useful links/articles/tips/tricks on System Verilog/VMM/OVM as and when I stumble upon them and some of my views on it :)

Deep vs Shallow Copy in SystemVerilog

This is another interesting aspect of SV, which beginners usually get confused. This is an excellent blog post @ trusser on the same.

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I am from Sambalpur, Orissa, India. Have done Btech and Mtech in ECE from IIT Kharagpur. Currently working as Lead Member Technical Staff at Mentor Graphics Noida

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