The Ultimate Hitchhiker's Guide to Verification

Dumping ground of useful links/articles/tips/tricks on System Verilog/VMM/OVM as and when I stumble upon them and some of my views on it :)

Best sites to Learn System Verilog

There are large numbers of sites which have materials of system verilog, reading which you can learn it. But, there are few really good site, where system verilog has been described in a real nice way, and you have a smooth ride while learning SV. I personally learned from them quite a bit of system verilog from these sites.

  1. Testbench.in : System Verilog and VMM tutorial with a lots of example
  2. Asicguru.com : Another nice SV tutorial site
  3. Doulos SV Tutorial : Not that much extensive, but still good
  4. Another decent tutorial from Project-Veripage
  5. SV Tutorial from ASIC-World. It is not yet complete, but once it is complete, then it will be another great site to learn SV.
Amongst all 4, testbench.in is the best. It's a 10/10 site, you visit it, start learning and will fall in love with it. I feel proud of the fact that the creator of the site Gopi Krishna is from India. Way to go Gopi.

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I am from Sambalpur, Orissa, India. Have done Btech and Mtech in ECE from IIT Kharagpur. Currently working as Lead Member Technical Staff at Mentor Graphics Noida

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