The Ultimate Hitchhiker's Guide to Verification

Dumping ground of useful links/articles/tips/tricks on System Verilog/VMM/OVM as and when I stumble upon them and some of my views on it :)

Explain the difference between data types logic and reg and wire

Ans:-
To answer this I am not assuming the reader knows the answer for the difference between wire and reg.

Wire:-

  1. Wires are used for connecting different elements
  2. They can be treated as a physical wire
  3. They can be read or assigned
  4. No values get stored in them
  5. They need to be driven by either continuous assign statement or from a port of a module
Reg:-
  1. Contrary to their name, regs doesn't necessarily corresponds to physical registers
  2. They represents data storage elements in Verilog/SystemVerilog
  3. They retain their value till next value is assigned to them (not through assign statement)
  4. They can be synthesized to FF, latch or combinational circuit (They might not be synthesizable !!!)
Wires and Regs are present from Verilog timeframe. SystemVerilog added a new data type called logic to them. So the next question is what is this logic data type and how it is different from our good old wire/reg.

Logic:-
  1. As we have seen, reg data type is bit mis-leading in Verilog. SystemVerilog's logic data type addition is to remove the above confusion. The idea behind having a new data type called logic which at least doesn't give an impression that it is hardware synthesizable
  2. Logic data type doesn't permit multiple driver. It has a last assignment wins behavior in case of multiple assignment (which implies it has no hardware equivalence). Reg/Wire data type give X if multiple driver try to drive them with different value. Logic data type simply assign the last assignment value.
  3. The next difference between reg/wire and logic is that logic can be both driven by assign block, output of a port and inside a procedural block like this
    logic a;
    assign a = b ^ c; // wire style
    always (c or d) a = c + d; // reg style
    MyModule module(.out(a), .in(xyz)); // wire style


Reference:-
  1. Cliff's article on the same
  2. Discussion on the same at Verification Guild

3 comments:

java July 20, 2011 at 9:31 PM  

nicely described ! thanks!!

أسامة April 10, 2012 at 8:45 AM  

Thank you!
Nice description and structured!

Dipesh Handa July 12, 2012 at 11:36 PM  

Very informative..Thanks..!!

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