I most confess, I have become a very big fan of SystemVerilog `define macro for the amount of effort I save because of using it. The big advantage of using this is that you can concisely describe your intention in a more readable (and less SystemVerilog syntax) using macro. Another advantage is you need to change only at one place if you find out that you need to change the expression you have used in 100 of places. The 3rd reason is that it is widely used in industry. Some example worth quoting are
- Using SystemVerilog Assertions for Functional Coverage
- Using SystemVerilog Assertions for Creating Property-Based Checkers
- SystemVerilog Assertions Design Tricks and SVA Bind Files
- VMM and especially VMM data macro
Ans : Web (thanks to the all powerful demi-god of internet ... Google)
- http://www.google.co.in/#hl=en&safe=off&q=Systemverilog+Macro
- System Verilog LRM 3.1a : Section : 25.2
- Sandeep Vaniya's Advanced Use of define macro in SystemVerilog (not so advanced actually !!!)
// Example macro for a coverage class
// Aim : want to get ABC_cp : coverpoint ABC {bins b = {1}; }
// by calling `COV(ABC)
`define COV(__name) __name``_cp : coverpoint __name {bins b = {1}; }
// Next
// What to do if I want cp_ABC in place of ABC_cp as for the above example
// NOTE : I can't use cp_``__name as cp_ is not an input to the macro
// Solution
// Use nested macros
`define PREFIX(__prefix, __name) __prefix``__name
`define COV2(__name) `PREFIX(cp_,__name) : coverpoint __name {bins b = {1}; }
Nested macro is not a new thing in SV. They are being extensively used in VMM data macro class. But no example of nested macro and achieving of addition pre_fix to variable name in `define macro is bit puzzling to me. I tried the above in vcs and seems to work perfectly fine.Next, where not to use `define (SV other better alternatives to `define these cases)
