Deep vs Shallow Copy in SystemVerilog

This is another interesting aspect of SV, which beginners usually get confused. This is an excellent blog post @ trusser on the same.

• Deep versus Shallow Copy
  

Some interesting ways to get a delayed version of signal in SV

In TB world, sometime you will need a signal which is N clock delayed version of another signal. You can do it by using 9 intermediate variables, or use these.

// I want 10 clock delayed version of signal abc
always @(posedge clk) begin
    abc_10_clk_delayed_1 <= $past(abc, 10); // This works in vcs
    abc_10_clk_delayed_2 <= repeat(10) @(posedge clk) abc;
end