Few nice articles on UVM

• A Practical Guide to Adopting the Universal Verification Methodology—Part 1
  
• A Practical Guide to Adopting the Universal Verification Methodology—Part 2
  
• A Practical Guide to Adopting the Universal Verification Methodology—Part 3
  
• A Practical Guide to Adopting the Universal Verification Methodology—Part 4
  

Easier UVM for Functional Verification by Mainstream Users :: From Doulos

http://www.doulos.com/knowhow/sysverilog/uvm/easier_uvm_paper/

How Do I Get Environment Variable into a String in SystemVerilog

From Synopsys Solvnet, Needs to have Solvnet id, seems to be specific to VCS

1. https://solvnet.synopsys.com/retrieve/032548.html?charid=techupdate&tuid=413