Answers to SystemVerilog Interview Questions - 4

(25)What is the difference between rand and randc?

 Ans:-
rand - Random Variable, same value might come before all the the possible value have been returned. Analogous to throwing a dice.

randc - Random Cyclic Variable, same value doesn't get returned until all possible value have been returned. Analogous to picking of card from a deck of card without replacing. Resource intensive, use sparingly/judiciously
 
(24)How to call the task which is defined in parent object into derived class ?
Ans:-
super.task_name();

(21)What is the difference between always_combo and always@(*)?
 Ans:-
 From SystemVerilog LRM 3.1a:-

1. always_comb get executed once at time 0, always @* waits till a change occurs on a signal in the inferred sensitivity list
2. Statement within always_comb can't have blocking timing, event control, or fork-join statement. No such restriction of always @*
3. Optionally EDA tool might perform additional checks to warn if the behavior within always_comb procedure doesn't represent combinatorial logic
4. Variables on the left-hand side of assignments within an always_comb procedure, including variables
   from the contents of a called function, shall not be written to by any other processes, whereas always @* permits multiple processes to write to the same variable.
5. always_comb is sensitive to changes within content of a function, whereas always @* is only sensitive to changes to the arguments to the function.

A small SystemVerilog code snippet to illustrate #5

module dummy;
    logic a, b, c, x, y;

    // Example void function
    function void my_xor;
        input a;           // b and c are hidden input here
        x = a ^ b ^ c;
    endfunction : my_xor

    function void my_or;
        input a;           // b and c are hidden input here
        y = a | b | c;
    endfunction : my_xor
    
    always_comb            // equivalent to always(a,b,c)
        my_xor(a);         // Hidden inputs are also added to sensitivity list

    always @*              // equivalent to always(a)
        my_or(a);          // b and c are not added to sensitivity list
endmodule

(20)List the predefined randomization methods.
  Ans:-

1. randomize
2. pre_randomize
3. post_randomize

(19)What is scope randomization ?
  Ans:-
  Scope randomization ins SystemVerilog allows assignment of unconstrained or constrained random value to the variable within current scope

module MyModule;      
integer var, MIN;      

initial begin          
    MIN = 50;          
    for ( int i = 0;i<10 ;i++) begin              
        if( randomize(var) with { var < 100 ; var > MIN ;})  
            $display(" Randomization sucsessfull : var = %0d Min = %0d",var,MIN);   
        else                  
            $display("Randomization failed");
    end
          
    $finish;     
end
endmodule

Answers to SystemVerilog Interview Questions - 3

(88)How to check weather a handles is holding object or not ?
Ans:-
It is basically checking if the object is initialized or not. In SystemVerilog all uninitialized object handles have a special value of null, and therefore whether it is holding an object or not can be found out by comparing the object handle to null. So the code will look like:-

usb_packet My_usb_packet; 
...
if(My_usb_packet == null) begin
    // This loop will get exited if the handle is not holding any object
    ....
end else begin
    // Hurray ... the handle is holding an object
    ...
end

(87)What is the difference between initial block and final block?
Ans:-
There are many difference between initial and final block. I am listing the few differences that is coming to mind now.

1. The most obvious one : Initial blocks get executed at the beginning of the simulation, final block at the end of simulation
2. Final block has to be executed in zero time, which implies it can't have any delay, wait, or non-blocking assignments. Initial block doesn't have any such restrictions of execution in zero time (and can have delay, wait and non-blocking statements)

Final block can be used to display statistical/genaral information regarding the status of the execution like this:-

final begin
    $display("Simulation Passed");
    $display("Final value of xyz = %h",xyz);
    $display("Bye :: So long, and Thanks for all the fishes");
end

(69)What is the difference between bits and logic?
Ans:-
bits is 2-valued (1/0) and logic is 4-valued (0/1/x/z)

(65)What is tagged union ?
Ans:-
An union is used to stored multiple different kind/size of data in the same storage location.

typedef union{
    bit [31:0]  a;
    int         b;
} data_u;

Now here XYZ union can contain either bit [31:0] data or an int data. It can be written with a bit [31:0] data and read-back with a int data. There is no type-checking done.

In the case where we want to enforce that the read-back data-type is same as the written data-type we can use tagged union which is declared using the qualifier tagged. Whenever an union is defined as tagged, it stores the tag information along with the value (in expense of few extra bits). The tag and values can only be updated together using a statically type-checked tagged union expression. The data member value can be read with a type that is consistent with current tag value, making it impossible to write one type and read another type of value in tagged union. (the details of which can be found in section 3.10 and 7.15 of SV LRM 3.1a).

typedef union tagged{
    bit [31:0]  a;
    int         b;
} data_tagged_u;

// Tagged union expression
data_tagged_u data1 = tagged a 32'h0;
data_tagged_u data2 = tagged b 5;

// Reading back the value
int xyz = data2.b;

(56)What is the need of alias in SV?
Ans:-
The Verilog has one-way assign statement is a unidirectional assignment and can contain delay and strength change. To have bidirectional short-circuit connection SystemVerilog has added alias statement. An excellent usage example of alias can be found out at http://www.systemverilog.org/pdf/SV_Symposium_2003.pdf(Slide # 59)

Few minor updates

Two small updates from my blog.

1. My blog has started getting attentions from Verification community. Recently my blog got added to blogroll of VMM martial art blog (http://www.vmmcentral.org/vmartialarts/). Seems people are finding my blog worth reading/visiting. My blog is feeling blessed :)
   
2. With almost 4-5 hrs of effort I could make syntaxhighlighter work (with small minor hiccups). It took way too much time as compared to what I hoped for, but the end result of it is worth it. A sample o/p from syntax highlighter.

// Byte Pack
function int unsigned atm_cell::byte_pack(ref logic [7:0] bytes[],
                                          input int unsigned offset,
                                          input int kind);
   // Make sure there is enough room in the array
   if(bytes.size() < this.byte_size())
        bytes = new [this.byte_size()] (bytes);
   // Pack the bytes
   bytes[0] = {gfc, vpi[7:4]};
   bytes[1] = {vpi[3:0], vci[15:12]};
   bytes[2] = {vci[11:4]};
   bytes[3] = {vci[3:0], pt, clp};
   bytes[4] = {hec};
   for (int i=0; i < 48; i++)
     bytes[i+5]=payload[i];
   byte_pack = 53;
endfunction

// Byte Unpack
function int unsigned atm_cell::byte_unpack(const ref logic[7:0] bytes[],
                                            input int unsigned offset,
                                            input int len,
                                            input int kind);
   {gfc, vpi, vci, pt, clp, hec} = {bytes[0], bytes[1], bytes[2],
                                     bytes[3], bytes[4]};
   for (int i = 0; i != 48; ++i)
     payload[i] = bytes[i+5];

   return 53;
endfunction

All about fork-join of System Verilog

I have added histstat hit counter for my blog to have an idea about traffic/visitor/search engine trends. One interesting I am observing is that quite a few hit to my site is coming for fork/join interview questions in Google. Hence I thought, why not have a real useful post on fork/join{x} of SystemVerilog and its associated disable/wait command.

Fork-join statement has come from Verilog. It is used for forking out parallel processes in test bench. SV substantially improved fork/join construct to have much more controllability in process creation, destruction, and waiting for end of the process.

The basic syntax of fork join block looks like this:

fork
   begin : First_thread
       // Code for 1st thread
   end
   begin : Second_thread
       // Code for 2nd thread
   end
   begin : Third thread
       // Code for 3rd branch
   end
   ...
join    // Can be join_any, join_none in SV

There are 3 different kind of join keyword in SV, each specifying a different way of waiting for completion of the threads/process created by the fork.

• join : waits for completion of all of the threads
• join_any : waits for the completion of the 1st thread, then comes out of fork loop, but lets the other process/thread execute as usual
• join_none : doesn't wait for completion of any thread, just starts then and immediately exits fork loop.

Now, suppose you have exited the fork loop by join_none or join_any and after some steps, you want to wait till completion of all the threads spanned by the previous fork loop. SV has "wait fork" for the same.

Now, suppose you have exited the fork loop by join_none or join_any and after some steps, you want to kill all the threads spanned by the previous fork loop. SV has "disable fork" for the same.

Next interesting scenario: you have exited fork loop by join_none or join_any and after some steps, you want to kill just one thread (out of many). The solution, have named begin end block and call "disable ". (For example, in the last example if you want to kill only the 2nd thread after exiting the loop via join_any/join_none, then add "disable Second_thread;" at the point where you want to disable the second thread.

I have created a image to pictorially depict fork/join in SV. Hope that will help understand this in a much better way.

VMM shorthand macros

Those who have worked with VMM based verification environment must have encountered situation where you need to code the different essential functions of vmm_data class like copy, psdisplay, compare and so on. This task become very tedious/boring when the number of classes you need to code is substantial, each having lengthy list of data member. Not long back, to get rid of the monotonicity of the above task, I sat for a day and wrote a perl script to generate the complete vmm_data class with essential functions from a class template.

Well, my one day effort is fixing the same is not worth the effort, as VMM has in-built short-hand-macros to solve it. It's especially useful when you don't have much non-standard data type (which are not supported by VMM shorthand macro)

class sample_class extends vmm_data;

// Simple scalar types
rand bit [7:0] da;
rand bit [8:0] db [10];
rand bit       dc [];
rand bit       dd [int];
rand bit       de [string];

...
‘vmm_data_member_begin(sample_class)
‘vmm_data_member_scalar(da, DO_ALL)         
‘vmm_data_member_scalar_array(db, DO_ALL)   
‘vmm_data_member_scalar_da(dc, DO_ALL)      
‘vmm_data_member_scalar_aa_scalar(dd, DO_ALL)
‘vmm_data_member_scalar_aa_string(de, DO_ALL)
‘vmm_data_member_end(sample_class)
...
endclass : sample_class

Some salient features of VMM shorthand macros are :

1. They can be used for {scalar, string, enums, vmm_data, handles} x {normal, array, dynamic array, associative array (scalar, and string type)} combination (Total 25 types)
   
2. These shorthands are valid for classes derived from vmm_data, vmm_env, vmm_subenv, vmm_xactor, and vmm_scenario
3. The function which will get implemented depends upon what class your class is being instantiated from.
   
4. For unlucky data member which doesn't fall into these 25 category, you can specify the same using `vmm_data_member_user_defined macro

What I have presented here is a very high level overview of the feature and in no way complete. For interested user please refer these links for complete details:-

• http://www.vmmcentral.org/onlinedoc/wwhelp/wwhimpl/js/html/wwhelp.htm#href=02_shorthands.3.1.html
• http://www.vmmcentral.org/onlinedoc/wwhelp/wwhimpl/js/html/wwhelp.htm#href=UG_AppendixA.7.97.html
  

Explain the difference between data types logic and reg and wire

Ans:-
To answer this I am not assuming the reader knows the answer for the difference between wire and reg.

Wire:-

1. Wires are used for connecting different elements
2. They can be treated as a physical wire
3. They can be read or assigned
4. No values get stored in them
5. They need to be driven by either continuous assign statement or from a port of a module

Reg:-

1. Contrary to their name, regs doesn't necessarily corresponds to physical registers
2. They represents data storage elements in Verilog/SystemVerilog
3. They retain their value till next value is assigned to them (not through assign statement)
4. They can be synthesized to FF, latch or combinational circuit (They might not be synthesizable !!!)

Wires and Regs are present from Verilog timeframe. SystemVerilog added a new data type called logic to them. So the next question is what is this logic data type and how it is different from our good old wire/reg.

Logic:-

1. As we have seen, reg data type is bit mis-leading in Verilog. SystemVerilog's logic data type addition is to remove the above confusion. The idea behind having a new data type called logic which at least doesn't give an impression that it is hardware synthesizable
2. Logic data type doesn't permit multiple driver. It has a last assignment wins behavior in case of multiple assignment (which implies it has no hardware equivalence). Reg/Wire data type give X if multiple driver try to drive them with different value. Logic data type simply assign the last assignment value.
   
3. The next difference between reg/wire and logic is that logic can be both driven by assign block, output of a port and inside a procedural block like this

   logic a;
   assign a = b ^ c;                   // wire style 
   always (c or d) a = c + d;          // reg style
   MyModule module(.out(a), .in(xyz)); // wire style

Reference:-

1. Cliff's article on the same
2. Discussion on the same at Verification Guild
   

SystemVerilog OOP links

Here are some nice OOP links on SystemVerilog OOP which can be used as a good starting point/reference.

1. Object Oriented Programming for Hardware Verification
   
   


2. Improve Your SystemVerilog OOP Skills by Learning Principles and Patterns
3. SystemVerilog OOP OVM Feature Summary
   
   
   SystemVerilog OOP Ovm Features Summary

   View more presentations from Amal Khailtash.
   
   
4. Enhancing SystemVerilog with AOP Concepts (On how to mimic AOP features in OOP, good for guyz coming from e background)
5. Testbench.in OOP Tutorial