Some interesting ways to get a delayed version of signal in SV

In TB world, sometime you will need a signal which is N clock delayed version of another signal. You can do it by using 9 intermediate variables, or use these.

// I want 10 clock delayed version of signal abc
always @(posedge clk) begin
    abc_10_clk_delayed_1 <= $past(abc, 10); // This works in vcs
    abc_10_clk_delayed_2 <= repeat(10) @(posedge clk) abc;
end

VMM shorthand macros

Those who have worked with VMM based verification environment must have encountered situation where you need to code the different essential functions of vmm_data class like copy, psdisplay, compare and so on. This task become very tedious/boring when the number of classes you need to code is substantial, each having lengthy list of data member. Not long back, to get rid of the monotonicity of the above task, I sat for a day and wrote a perl script to generate the complete vmm_data class with essential functions from a class template.

Well, my one day effort is fixing the same is not worth the effort, as VMM has in-built short-hand-macros to solve it. It's especially useful when you don't have much non-standard data type (which are not supported by VMM shorthand macro)

class sample_class extends vmm_data;

// Simple scalar types
rand bit [7:0] da;
rand bit [8:0] db [10];
rand bit       dc [];
rand bit       dd [int];
rand bit       de [string];

...
‘vmm_data_member_begin(sample_class)
‘vmm_data_member_scalar(da, DO_ALL)         
‘vmm_data_member_scalar_array(db, DO_ALL)   
‘vmm_data_member_scalar_da(dc, DO_ALL)      
‘vmm_data_member_scalar_aa_scalar(dd, DO_ALL)
‘vmm_data_member_scalar_aa_string(de, DO_ALL)
‘vmm_data_member_end(sample_class)
...
endclass : sample_class

Some salient features of VMM shorthand macros are :

1. They can be used for {scalar, string, enums, vmm_data, handles} x {normal, array, dynamic array, associative array (scalar, and string type)} combination (Total 25 types)
   
2. These shorthands are valid for classes derived from vmm_data, vmm_env, vmm_subenv, vmm_xactor, and vmm_scenario
3. The function which will get implemented depends upon what class your class is being instantiated from.
   
4. For unlucky data member which doesn't fall into these 25 category, you can specify the same using `vmm_data_member_user_defined macro

What I have presented here is a very high level overview of the feature and in no way complete. For interested user please refer these links for complete details:-

• http://www.vmmcentral.org/onlinedoc/wwhelp/wwhimpl/js/html/wwhelp.htm#href=02_shorthands.3.1.html
• http://www.vmmcentral.org/onlinedoc/wwhelp/wwhimpl/js/html/wwhelp.htm#href=UG_AppendixA.7.97.html
  

SV Tips/Tricks - Converting Strings to Enums

SystemVerilog enumerated data type has one major shortcoming namely the inability to covert string to enum data type, whereas the reverse is possible. But there are many cases when one find the need to do so. Thankfully JL Gray of verilab has created a sample class template which can be used for the same purpose. The link to the blog entry is

http://www.verilab.com/blog/2007/10/casting-strings-to-enums-in-systemverilog/

Enjoy maadi !!