The Ultimate Hitchhiker's Guide to Verification

Slides from DVCon UK 2011

2011-11-28T03:31:00.001-08:00

http://www.testandverification.com/downloads/DVConference2011/

Pointer to UPF standard online

2011-11-25T02:30:00.001-08:00

UPF 1.0 standard

Unified Power Format (UPF) Standard

UPF 2.0 standard via scribd. Can be viewed online.

http://www.scribd.com/doc/59271855/1801-2009-v-2-0

A nice blog on Power Aware Verification/UPF

2011-11-17T01:44:00.001-08:00

Today I came across a nice blog on UPF/Low Power. Sharing it

Magic Blue Scope

Mentor Graphics NOIDA is hiring.

2011-09-19T04:13:00.000-07:00

Please mail me your resume at subash.nayak@gmail.com if you want to apply to any of the below jobs.

One small update

2011-09-14T05:01:00.000-07:00

Hi all,

To begin with let me thank all for visiting my blog. I have got many feedback on how people (few whom I know personally, and many I don't know) have used my blog for learning SV and preparing for job interviews. It feel good knowing that I have contributed something positively (a very little, I know :)) to the society via my blog.

There is a small news to share with you all. Recently I have joined Mentor Graphics NOIDA as LMTS, where I am involved in tool development effort. So it is hardcore C++ coding/debug for me, and very little SystemVerilog/Verification. So from now on I am planning to blog on C/C++/SW development mostly, little less SV.

Regards,
-Subash

Wavedrom : Web based Waveform editor

2011-06-22T07:19:00.001-07:00

http://code.google.com/p/wavedrom/

Few nice articles on UVM

2011-05-17T23:01:00.000-07:00

Easier UVM for Functional Verification by Mainstream Users :: From Doulos

2011-05-10T22:20:00.000-07:00

http://www.doulos.com/knowhow/sysverilog/uvm/easier_uvm_paper/

How Do I Get Environment Variable into a String in SystemVerilog

2011-05-04T01:03:00.000-07:00

From Synopsys Solvnet, Needs to have Solvnet id, seems to be specific to VCS

https://solvnet.synopsys.com/retrieve/032548.html?charid=techupdate&tuid=413

Some interesting article on Verification

2010-12-02T21:11:00.000-08:00

These are some nice article on verification, that I stumbled upon. Hope it will be useful for the reader

Doing "cvs add" recursively

2010-11-26T03:25:00.000-08:00

Those who are still stuck with the age-old CVS due to some unfortunate reason (in the age of Perforce ...), they must have encountered situations when they want to add multiple files/folders recursively. This is one command I found via google search which will help in such situation
.

  find . -type d -print | grep -v CVS | xargs cvs add
  find . -type f -print | grep -v CVS | xargs cvs add

Writing SystemVerilog assertion for checking "setup/hold time violation" type of conditions

2010-07-19T12:05:00.000-07:00

Recently, I gave couple of internal lectures on basic and advanced features of SystemVerilog assertion at the organization that I am working at. After that, quite a few colleague of mine have started asking questions on SVA. Amongst all, the most interesting assertion question is how to write assertion for checking "setup/hold time violation" type of scenarion. To understand these scenario, let's start with a very common example, which can be extended for many similar case.

Problem statement:

Write assertion for checking that the signal "data" is stable for tSetup time before positive edge of clock, and should be stable for tHold time after positive edge of clock. Here tSetup/tHold will be of static delay like 1ns, 30ps or so on. There are no extra inherent assumptions added with it (like clock period, its relationship with tSetup/tHold, or how fast the signal data can toggle.

This is a standard problem, with not so easy solution of writing assertion for it

In Verilog there is a way of checking it, which unfortunately is not an assertion, and hence can't be used with formal tools like Jasper. (via http://www.edaboard.co.uk/requesting-help-on-writing-sv-assertions-t442372.html http://www.edaboard.co.uk/requesting-help-on-writing-sv-assertions-t442372.html)

module timing_checks (input clk, en); 
  specify 
    specparam clk_high_time = 5; 
    specparam clk_low_time = 5; 
    $setup(en, negedge clk, clk_high_time * 4 / 5); 
    $hold(negedge clk, en, clk_low_time * 4 / 5); 
  endspecify 
endmodule

Now let's proceed with assumption that we want to write an assertion for checking the same, we are not very much happy with $setup/$hold of Verilog. Here is the solution

module timing_checks_in_sv (input clk, data, ...); 
  ...
  event ev_data_delayed_toggled;
  
  always @(data)
  begin
    fork
    begin
      # tSetup;
      -> ev_data_delayed_toggled;
    end
    join_none
  end

  property setup_hold_time_checker;
    time curr_time;
    @(posedge clk) (1, curr_time = $time) |->
    @(ev_data_delayed_toggled) (($time - curr_time) > (tSetup + tHold));
  endproperty : setup_hold_time_checker

  ASSERT_SETUP_HOLD: assert property setup_hold_time_checker;
endmodule

In the always block, we are triggering an event called ev_data_delayed_toggled, after tSetup time every time data toggles. Now the "setup/hold time" problem statement can be written as after posedge of clock, ev_data_delayed_toggled shouldn't get triggered within tSetup+tHold time. Now the problem statement has come to a form SVA timing check, which is specified in via the property.

There are many such not so intuitive, interesting use-case scenarios for SVA. Interested readers can have a look at the below link for some more interesting scenarios.

http://www.verilab.com/files/sva_gate_paper_dvcon2006.pdf

System Verilog Fine Grain Process Control - They are actually used in standard methodologies

2010-07-18T03:33:00.000-07:00

Thanks to 2 articles in one Japanese blog, and google translate, I got to know that fine grain process control are use sparingly (mostly for process kill) in OVM/VMM. I am just pasting the link of these article in the hope that interested reader shall go through them, do some more research and get himself enlightened with the usage of fine grain process control of systemverilog.

Advanced SystemVerilog Process Control – Beyond fork-join_X

2010-07-09T11:09:00.000-07:00

Abstract— All the Hardware Verification Languages (HVL) have an inherent requirement to have process control capabilities like creation, control and destruction of process. Although Verilog language has incorporated such capabilities like named blocks and fork-join statements, but SystemVerilog has further extended these properties of verilog with introduction of fork-join_X, disable fork and fine grain process control. ―Fine grain process control is the least understood and least used capability amongst all the SystemVerilog process control capabilities. The main reason behind the same is due to the fact that SV LRM[1] has very brief and concise description (about two pages) of fine grain process control. This paper aims in de-mystifying the above constructs and shows the use of fine grain process control for much more flexible processes creation, their control as well as destruction capabilities. It discusses how per-instance-based process control and decoupling of ―how and when can be done using SV fine grain process control

Index Terms—Fine grain process control, Inbuilt process class of SystemVerilog, Per-instance based process control, Decoupling of how and when of processes.

I. INTRODUCTION

Process control capabilities like creation, control and destruction of processes are inherent requirements of any Hardware Verification Language. Verilog has named block, fork-join construct for controlling process creation, control and destruction. Below example will show some of the capabilities of verilog process control.

always @(posedge req) begin 
  fork 
  begin : Label1 
    wait(a); 
    disable Label2; 
  end 
  begin : Label2 
    wait(b); 
  end 
  join 
end

In the above mentioned code snippet, we are creating two threads named “Label1” and “Label2” at every posedge of req. In the thread “Label1”, as soon as signal “a” becomes HIGH, it kills the thread “Label2”.

But, there are few limitations in Verilog’s process creation, control as well as destruction. The main limitation of verilog’s fork-join statement is that there is very less flexibility in terms of when it should get out of fork loop. In addition, disabling of named block is not a good way of killing a process.

SystemVerilog solved the 1st limitation of verilog’s process control capabilities by adding new constructs like join_any, join_none, disable fork and wait fork. These constructs are widely used for controlling process creation/control/destruction.

However these constructs have further few limitations for finer control of process. Using the above constructs, we cannot suspend/resume/kill only a specific single process. SystemVerilog has a feature called “Fine grain process control” using which we can have much finer control on creation/control/destruction of process.

II. FINE GRAIN PROCESS CONTROL
Fine grain process control is meant for having finer control on processes compared to the control one can get using fork/join_x constructs. This is done using SystemVerilog’s inbuilt class called ’process’. Let’s look at the various feature of the above class and how to use them for finer control of processes.

A. Handle Creation and status check
To control any process/thread, we need to get the handle of the above thread using calling “process::self()” method of process class. Below code snippet will show how to do the same.

task abc(…); 
  process P; 
  process::state Pstate; 
  … 
  fork 
  begin 
    P = process::self(); 
    … 
    Pstate = P.status(); 
  end 
  join_none 
endtask : abc

A process can be created for each always, initial block, and begin…end statement inside fork…join_X and dynamic processes. In addition, we can check the status of any process by calling status() method. A process can be in either of these 5 states (FINISHED, RUNNING, WAITING, SUSPENDED, KIL). “process::state” is a enumerated value and its content can be displayed using .name() method.

B. Process Suspension, Resumption, Await and Kill
Any process can be suspended or resumed by calling suspend() and resume() task of process class. Similarly, the process can be terminated by calling kill() method. The await() method blocks till the process is terminated. SystemVerilog code snippet given in section “USE-CASE: FINER CONTROL OF PROCESS”.

There can be few race conditions when a process is waiting for some event/variable change and we suspend the process. The question is on what condition the process shall resume its execution. These are simple rules to know when the process shall get unblocked from the waiting event[2]

If the process is waiting for a delay like (#100 or #20ns) while going to suspend state, it will not count the time spent while in suspend state as the delay.
If the process is waiting for an event (@(SV_event)) while going for suspend state, and the event has occurred when the process is at suspend state, then the process will be unblocked, and will start executing from the next while after resuming.
If the process is waiting for variable change (@(SV_variable) or wait(SV_variable)) : Check for change of the variable is not performed when the process is suspended and hence any variable change happened during the time when the process is in suspended state shall not unblock the process if it is waiting for variable change and is put to suspend state

III. USE-CASE: PER-INSTANCE BASED FINER CONTROL OF PROCESSES.
Consider a scenario where we have created some N numbers of thread/process in one task. From another task, we want to suspend/resume/kill selected few tasks depending upon some other external conditions. Fine grain process control is extremely well suited for these kinds of tasks. Let see an example code snippet to understand how it can be done.

class fine_grain_process_ctrl_example;
 
  // Data members
  process p[20];        
  …

  task spawn_thread;
    for(int i=0; i<20; i++)
    begin
      fork
      begin
        p[i] = process::self();
        run_thread();
      end
      join_none
    end       
  endtask: spawn_thread
 
  task control_thread;
    …
    // condition met for suspending p[i]
    p[i].suspend();
    …
    // condition met for resuming p[j]
    p[j].resume();
    …
    // condition met for killing p[k]
    p[k].kill();
    …
    // Wait for completion of p[l]
    p[l].await();
  endtask: control_thread
endclass: fine_grain_process_ctrl_example

In the above code snippet, we have a class called fine_grain_process_ctrl, which has an array of process handles. In the task spawan_thread, where we are creating 20 parallel threads (by calling some external task run_thread()), we are also storing the handle of the process into the process array. Now in the task control_thread, we are controlling the suspension/resumption/termination of the above threads (which can be done in per-instance basis) depending upon some condition).

There is another advantage of the above way of doing the process control. Here effectively, we are de-coupling what to do in the thread, and how to handle thread. This decoupling is very useful for code-reuse. The details of the above aspect are described in more detail in next section.

IV. USE-CASE: DECOUPLING HOW AND WHEN

Consider a case where you have already written a transactor which sends packets according to your requirements. Now you need to change your code to make it work in the low-power-world where you need to stop sending packets whenever the system enters low-power state and resume sending packet once you are out of it. You have coded “HOW” to send your packet, and now you need to incorporate “WHEN” to send it, which itself can be far more complex that the simple “HOW”.

You can directly go and modify the transactor code to incorporate “WHEN” aspect of the packet transmission. There are quite a few reasons why you would rather not touch the code and do the same in another way.

Fine grain process control can be very nicely used in such scenario. You can have a handle of the process of sending packet. Now using this handle, we can stop/resume execution of the process (thereby stopping/resuming sending of packet) by calling suspend/resume method. We can have another piece of code where we can code the logic which will have the logic that shall control “WHEN” to send the packet.

REFERENCES
[1] "IEEE Standard For SystemVerilog - Unified Hardware Design, Specification and Verification Language," IEEE Computer Society, IEEE, New York, NY, IEEE Std 1800-2009
[2] Article on “Fine Grain Process Control” at Synopsys Solvenet

System Verilog Fine Grain Process Control - Beyond SV LRM - Part I

2010-04-03T12:07:00.000-07:00

There is exactly 1 and 1/2 page long section on "Fine grain process control" is SV LRM (along with not so easy to follow example). No wonder I have not seen much people using this nice feature of System Verilog. Fortunately Synopsys SolvNet has 3 nice article on it. I am listing them for reference. Hope it shall be useful to the reader. (NOTE : accessing these articles requires solvnet login, which I was told, is not so easy to obtain unless your organization has a vcs license, the truthfulness of which I have not yet verified)

SN	Article Title
1	Fine Grain Process Control: Handle Creation & Status Check
2	Fine Grain Process Control: Process Await & Kill
3	Fine Grain Process Control: Process Suspend & Resume

Have you ever heard of a programming language called "Whitespace"?

2010-03-29T07:17:00.000-07:00

The question of the day is "Have you ever heard of a programming language called Whitespace?". If the answer is no then please refer to wikipedia article on in. Quoting directly from wikipedia for the lazy ones who would rather like to stay at this page rather than visit the wikipedia site

Whitespace is an esoteric programming language developed by Edwin Brady and Chris Morris at the University of Durham (also developers of the Kaya programming language). It was released on 1 April 2003 (April Fool's Day). Its name is a reference to whitespace characters. Unlike most programming languages, which ignore or assign little meaning to most whitespace characters, the Whitespace interpreter ignores any non-whitespace characters. Only spaces, tabs and linefeeds have meaning.^[1] An interesting consequence of this property is that a Whitespace program can easily be contained within the whitespace characters of a program written in another language, making the text a polyglot.^{[citation needed]}

Next question that shall be naturally occurring to you, why am I posting a link of some arbit/useless language in a blog which is devoted to verification. To answer this, I shall begin by asking you to find out the error in this code. Assume x, y, z to be simple logic variable.

`define SWAP(__a, __b) \
    __a = __a ^ __b;   \
    __b = __a ^ __b;   \ 
    __a = __a ^ __b; 

...
`SWAP(x,y)
`SWAP(y,z)
...

Couldn't find any issue with it. Let me show the above example with white space character as [space].

`define SWAP(__a, __b) \
    __a = __a ^ __b;   \
    __b = __a ^ __b;   \[space]
    __a = __a ^ __b; 

...
`SWAP(x,y)
`SWAP(y,z)
...

Now the issue is the extra white space character after \ of the SWAP macro definition. VCS doesn't like it and give some weird error which doesn't even tell that the error is due to the white-space after the \. I checked SV LRM and as per my understanding of reading the relevant section, it seems to be a valid system verilog code.

It took me half a day of banging my head in front of my monitor to find out that the issue is this extra whitespace after \ in the macro.

I feel Synopsys folks should do one of the following to make sure that no one else waste his precious time in debugging such hard-to-debug not-so-obvious issue.

Ignore whitespce after \ in multi-line macro definition OR
In case when a whitespace is encountered after \ in a multi-line macro, give error specifying that a whitespace character is encountered after \

Anyone from Synopsys listening ???

What is Factory Pattern - v2.0

2010-03-10T09:03:00.000-08:00

This post is a extended version of my original post on factory pattern which can be found at http://learn-systemverilog.blogspot.com/2009/08/what-is-factory-pattern.html

If you are working in System Verilog/VMM environment, it is high likely that you will be bombarded with word/expression from OOP world like "Factory Pattern", "Facade Pattern", "Observer Pattern" and so on. There is a finite possibility that you will seat down and start thinking what does those word mean and why they were used too frequently. Let me try to explain the idea/concept behind such word in the simplest way possible.

In SW engineering, a design pattern (or simply pattern) means a general repeatable solution to a commonly occurring problem. Most of these patterns have similarity to something or other in human society and hence they are known by that name.

Factory pattern as the name suggest, is aimed at solving the issue of creation of object. (Factory pattern is not the only pattern to deal with creation of objects, there are a bunch of more patterns for handling different kind of cases, and collectively they are known a creational patterns)

Let me give an example of case where we might need to use creational pattern and how to do so it in SV. Suppose you want to create a "Toy Factory" class which needs to create multiple types of toys (say toy aeroplane, toy tank, toy bus) depending upon the string input to it.

To create these different types of toys we need to have class defined for them. And there will be common method and data interface for these classes, hence it make sense to put all the common data member/task/functions in a class called toy class and then extend it.

class TOY;
    // Common data memeber
    string toy_name;

    // Common methods
    virtual function string get_type();
endclass : TOY

class TOY_Tank extends TOY;
    function new();
        this.toy_name = "Toy Tank";
    endfunction : new

    string function string get_type();
        return this.toy_name;
    endfunction : get_type
endclass : TOY_Tank

class TOY_Bus extends TOY;
    function new();
        this.toy_name = "Toy Bus";
    endfunction : new

    string function string get_type();
        return this.toy_name;
    endfunction : get_type
endclass : TOY_Bus

Now we are done with the bothering about the objects to be created. The next problem that we need to solve is to write the toy factory class itself. For simplicity, let's consider the case where we will want to pass 1 to get an instance of tank class and 2 for getting an instance of bus class from the factory. Now the factory class will look like this.

class TOY_factory;
    Toy my_toy

    // Common methods
    function toy get_toy(string str);
        if(str == "Toy Tank") this.my_toy = new TOY_Tank();
        if(str == "Toy Bus")  this.my_toy = new TOY_Bus();
        return this.my_toy;
    endfunction : get_toy
endclass : TOY_factory

Note that we are using virtual function for bringing polymorphism in action and save us from having an individual instance of the toy type in the factory class.

Reference

Factory Method Design Pattern from sourcemaking.com
Factory Method Pattern from wikipedia
Factory Pattern from JAVA design pattern

Note
Mike Mintz has added the following word of caution/note for this in the thread http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=3763

The above link is very good. I would just like to add a word of caution. The factory pattern should be rather rare in your architecture. While the choice of where to put the "new" for a class is very important, most of the time (for big components) the answer is in the testbench. That's where all the drivers,generators,monitors, etc should be built.

Also the factory pattern is usually implemented as a function, not a class. When it's a class, you can get sloppy with the necessary parameters and you code is harder to follow.

I understand pretty well the warping of these cautions caused by the three letter methodologies and their misguided quest for generic components, so your usage may have to follow their guidelines. Just remember that (1) in the real world factory patterns are rare, and (2) you do not always have to do it the way the methodology says.

SystemVerilog-201x listening campaign - Brad are you still listening !!!

2010-03-07T10:07:00.000-08:00

It seems recently the big guys in System Verilog (like Brad Pierce, just to give an idea of how big these guyz are) have decided to listen to people for possible improvement in System Verilog. The interested guy can check this page [http://bradpierce.wordpress.com/2009/12/14/systemverilog-201x-listening-campaign/] and give his/her "most likely" valuable comment and feel good about being a part of improving System Verilog to next level !!! (These kind of feel good are the only kind of feel good one can feel in these era of sub-prime induced recession, and similar economic artifacts) I have few idea/suggestion on improvement in SV to make it much more powerful/user friendly. I am listing them in the hope that someone might listen them and add them.

The keyword “singleton” for defining a class as singleton object. It shall get rid of the need of some weird way of getting singleton class in SV
```
singleton class  ABC;
…
endclass 
```
Unified verification methodology should be defined as a part of SV. There are way too many methodology now a days (like OVM, AVM, VMM and so on …). There should be one such standard methodology. It shall make life far easier for so many engineer.
SV macros are a very powerful tool for reducing the amount of coding effort. SV improved quite a bit on verilog macro, but still there is a quite a bit scope for improvement. `` is a very rudimentary operator. It can’t be used for adding prefix to the input of the macro. See the hack that we need to do for adding prefix at http://learn-systemverilog.blogspot.com/2009/09/system-verilog-define-macros-why-and.html
```
`define PREFIX(__prefix, __name) __prefix“__name
`define COV2(__name) `PREFIX(cp_,__name) : coverpoint __name {bins b = {1}; }
// should be something like
`define COV2(__name) cp_[[__name]] : coverpoint __name {bins b = {1}; } 
```
There is scope for adding macro programming ability to SV. It should have the ability of generating code during macro processing phase.
```
`for(int i=0; i<12; i++) begin \
bind module_1 module_2 bind_mod_[[i]] (.*); \
end 
```
Ability to get signal by passing the hierarchical reference to the signal like wire a = get_signal(top.dut.abc.xyz);

Option of crossing two cross coverage.

A : coverpoint ...
B : coverpoint ...
C : coverpoint ...
D : coverpoint ...

X : cross A, B;
Y : cross C, D;

// Z : cross X, Y; <----- SV doesn't allows it. It should

Free Timing Diagram Drawing tools

2010-03-06T22:32:00.000-08:00

Many a times we need to generate/draw timing diagrams for multitude purposes. While browsing web for the same I came across these free/easy-to-use timing diagram drawing utilities.

Timing Diagram Font -- Timing diagram can be generated in MS Word using this
Timing Analyzer -- A tool for doing the same

Timing Diagram from verilog - using the above tool and small snippet of verilog code, one can generate timing waveform from the design itself. One problem I see with it is that the code snippet doesn't use verilog macro for achieving the same.

Handy Timer - A simple and handy timing diagram editor
Timing Editor - Another free waveform editor
Draw Timing - Command line based waveform drawing SW which take a script as its input

Please let me know if you know some better/free timing diagram drawing tools that doesn't cost $$$.

Deep vs Shallow Copy in SystemVerilog

2009-11-28T04:54:00.000-08:00

This is another interesting aspect of SV, which beginners usually get confused. This is an excellent blog post @ trusser on the same.

Deep versus Shallow Copy

Some interesting ways to get a delayed version of signal in SV

2009-11-22T10:24:00.000-08:00

In TB world, sometime you will need a signal which is N clock delayed version of another signal. You can do it by using 9 intermediate variables, or use these.

// I want 10 clock delayed version of signal abc
always @(posedge clk) begin
    abc_10_clk_delayed_1 <= $past(abc, 10); // This works in vcs
    abc_10_clk_delayed_2 <= repeat(10) @(posedge clk) abc;
end

System Verilog `define macros : Why and how to use them (and where not to use!!!)

2009-09-19T11:04:00.000-07:00

I most confess, I have become a very big fan of SystemVerilog `define macro for the amount of effort I save because of using it. The big advantage of using this is that you can concisely describe your intention in a more readable (and less SystemVerilog syntax) using macro. Another advantage is you need to change only at one place if you find out that you need to change the expression you have used in 100 of places. The 3rd reason is that it is widely used in industry. Some example worth quoting are

Next question : Where shall I get the required info on how to use SystemVerilog `define macro
Ans : Web (thanks to the all powerful demi-god of internet ... Google)

http://www.google.co.in/#hl=en&safe=off&q=Systemverilog+Macro
System Verilog LRM 3.1a : Section : 25.2
Sandeep Vaniya's Advanced Use of define macro in SystemVerilog (not so advanced actually !!!)

From reading these it might be apparent that define macro can be used for adding a postfix to the variable, but not prefix. I was thinking the same after reading the description (they don't have a single example of adding prefix to the variable via `define. Confused ?? Let me explain by giving a concrete example

// Example macro for a coverage class
// Aim : want to get ABC_cp : coverpoint ABC {bins b = {1}; }
// by calling `COV(ABC)
`define COV(__name) __name``_cp : coverpoint __name {bins b = {1}; }

// Next
//     What to do if I want cp_ABC in place of ABC_cp as for the above example
//     NOTE : I can't use cp_``__name as cp_ is not an input to the macro

// Solution
//     Use nested macros
`define PREFIX(__prefix, __name) __prefix``__name
`define COV2(__name) `PREFIX(cp_,__name) : coverpoint __name {bins b = {1}; }

Nested macro is not a new thing in SV. They are being extensively used in VMM data macro class. But no example of nested macro and achieving of addition pre_fix to variable name in `define macro is bit puzzling to me. I tried the above in vcs and seems to work perfectly fine.

Next, where not to use `define (SV other better alternatives to `define these cases)

New Verilog-2001 Techniques for Creating Parameterized Models (or Down With `define and Death of a defparam!): Bit old but still usefull

Answers to SystemVerilog Interview Questions - 8

2009-09-14T09:53:00.000-07:00

13. What is the difference between mailbox and queue?
Ans:-
Mailbox are FIFO queue, which allows only atomic operations. They can be bounded/unbounded. A bounded mailbox can suspend the thread (while writing if full, while reading if empty) via get/put task. Thats why mailbox is well suited for communication between threads.

24. What is the use of $cast?
Ans:-
Typecasting in SV can be done either via static casting (', ', ') or dynamic casting via $cast task/function. $cast is very similar to dynamic_cast of C++. It checks whether the casting is possible or not in run-time and errors-out if casting is not possible.

27. What is $unit?
Ans:-
Refer these 2 doc form more details

http://www.systemverilog.org/pdf/SystemVerilog_Overall_31A.pdf
SV LRM 3.1a :: Section 18.3

28 .What are bi-directional constraints?
Ans:-
Constraints by-default in SystemVerilog are bi-directional. That implies that the constraint solver doesn't follow the sequence in which the constraints are specified. All the variables are looked simultaneously. Even the procedural looking constrains like if ... else ... and -> constrains, both if and else part are tried to solve concurrently. For example (a==0) -> (b==1) shall be solved as all the possible solution of (!(a==0) || (b==1)).

29. What is solve...before constraint ?
Ans:-
In the case where the user want to specify the order in which the constraints solver shall solve the constraints, the user can specify the order via solve before construct. i.e.

...
constraint XYZ  {
    a inside {[0:100]|;
    b < 20;
    a + b > 30;
    solve a before b;
}

The solution of the constraint doesn't change with solve before construct. But the probability of choosing a particular solution change by it.

40. What is circular dependency and how to avoid this problem ?
Ans:-
Over specifying the solving order might result in circular dependency, for which there is no solution, and the constraint solver might give error/warning or no constraining. Example

...
int x, y, z;
constraint XYZ  {
    solve x before y;
    solve y before z;
    solve z before x;
    ....
}

Answers to SystemVerilog Interview Questions - 7

2009-09-09T11:22:00.000-07:00

4. What is the need of clocking blocks ?
Ans:-
Clocking block in SystemVerilog are used for specifying the clock signal, timing, and synchronization requirements of various blocks. It separates the timing related information from structural, functional and procedural element of the TB. There are quite a few links on clocking block in the internet. These are links to learn about SV clocking blocks.

5. What are the ways to avoid race condition between testbench and RTL using SystemVerilog?
Ans:-
Short answer : -

Program block
Clocking block
Enforcement of design signals being driven in non-blocking fashion from program block

Long answer :-
Too long to describe here :). Please refer these doc/sections for more idea/info

7. What are the types of coverages available in SV ?
Ans:-
Using covergroup : variables, expression, and their cross
Using cover keyword : properties

12. What is the use of the abstract class?
Ans:-

http://www.testbench.in/CL_08_ABSTRACT_CLASSES.html

Answers to SystemVerilog Interview Questions - 6

2009-09-05T00:02:00.000-07:00

(30)Without using randomize method or rand,generate an array of unique values?
Ans:-

...
int UniqVal[10];
foreach(UniqVal[i]) UniqVal[i] = i;
UniqVal.shuffle();
...

(32)What is the difference between byte and bit [7:0]?
Ans:-
byte is signed whereas bit [7:0] is unsigned.

(33)What is the difference between program block and module?
Ans:-
Program block is newly added in SystemVerilog. It serves these purposes

It separates testbench from DUT
It helps in ensuring that testbench doesn't have any race condition with DUT
It provides an entry point for execution of testbench
It provides syntactic context (via program ... endprogram) that specifies scheduling in the Reactive Region.

Having said this the major difference between module and program blocks are

Program blocks can't have always block inside them, modules can have.
Program blocks can't contain UDP, modules, or other instance of program block inside them. Modules don't have any such restrictions.
Inside a program block, program variable can only be assigned using blocking assignment and non-program variables can only be assigned using non-blocking assignments. No such restrictions on module
Program blocks get executed in the re-active region of scheduling queue, module blocks get executed in the active region
A program can call a task or function in modules or other programs. But a module can not call a task or function in a program.

More details:-

http://www.testbench.in/SV_24_PROGRAM_BLOCK.html
http://www.project-veripage.com/program_blocks_1.php and few more next/next !!!
Section 16, SystemVerilog LRM 3.1a ... It's worth the effort reading line-by-line (and between the lines if you can :) ).

(37)What is the use of modports?
Ans:-
Modports are part of Interface. Modports are used for specifing the direction of the signals with respect to various modules the interface connects to.

...
interface my_intf;
    wire x, y, z;
    modport master (input x, y, output z);
    modport slave  (output x, y, input z);
endinterface

Please refer section 19.4 of SV LRM for more details

11. Explain about the virtual task and methods .
Ans:-
See http://www.testbench.in/CL_07_POLYMORPHISM.html

Answers to SystemVerilog Interview Questions - 5

2009-09-02T09:44:00.000-07:00

(9)What is inheritance and polymorphism?
Please refer these links for more details on inheritance/polymorphism.

(14)What data structure you used to build scoreboard?
Ans:-
Queue

(16)How parallel case and full cases problems are avoided in SV ?
Ans:-
See Page 34/35 of http://www.systemverilog.org/pdf/SV_Symposium_2003.pdf

(22)What is the use of package?
Ans:-
In Verilog declaration of data/task/function within modules are specific to the module only. They can't be shared between two modules. Agreed, we can achieve the same via cross module referencing or by including the files, both of which are known to be not a great solution.

The package construct of SystemVerilog aims in solving the above issue. It allows having global data/task/function declaration which can be used across modules. It can contain module/class/function/task/constraints/covergroup and many more declarations (for complete list please refer section 18.2 of SV LRM 3.1a)

The content inside the package can be accessed using either scope resolution operator (::), or using import (with option of referencing particular or all content of the package).

package ABC;
    // Some typedef
    typedef enum {RED, GREEN, YELLOW} Color;

    // Some function
    void function do_nothing()
        ...
    endfunction : do_nothing

    // You can have many different declarations here
endpackage : ABC

// How to use them
import ABC::Color;     // Just import Color
import ABC::*;         // Import everything inside the package

(26)What is $root?
Ans:-
$root refers to the top level instance in SystemVerilog

package ABC;
$root.A;       // top level instance A
$root.A.B.C;   // item C within instance B within top level instance A

Answers to SystemVerilog Interview Questions - 4

2009-08-28T12:12:00.000-07:00

(25)What is the difference between rand and randc?

Ans:-
rand - Random Variable, same value might come before all the the possible value have been returned. Analogous to throwing a dice.

randc - Random Cyclic Variable, same value doesn't get returned until all possible value have been returned. Analogous to picking of card from a deck of card without replacing. Resource intensive, use sparingly/judiciously

(24)How to call the task which is defined in parent object into derived class ?
Ans:-
super.task_name();

(21)What is the difference between always_combo and always@(*)?
Ans:-
From SystemVerilog LRM 3.1a:-

always_comb get executed once at time 0, always @* waits till a change occurs on a signal in the inferred sensitivity list
Statement within always_comb can't have blocking timing, event control, or fork-join statement. No such restriction of always @*
Optionally EDA tool might perform additional checks to warn if the behavior within always_comb procedure doesn't represent combinatorial logic
Variables on the left-hand side of assignments within an always_comb procedure, including variables
from the contents of a called function, shall not be written to by any other processes, whereas always @* permits multiple processes to write to the same variable.
always_comb is sensitive to changes within content of a function, whereas always @* is only sensitive to changes to the arguments to the function.

A small SystemVerilog code snippet to illustrate #5

module dummy;
    logic a, b, c, x, y;

    // Example void function
    function void my_xor;
        input a;           // b and c are hidden input here
        x = a ^ b ^ c;
    endfunction : my_xor

    function void my_or;
        input a;           // b and c are hidden input here
        y = a | b | c;
    endfunction : my_xor
    
    always_comb            // equivalent to always(a,b,c)
        my_xor(a);         // Hidden inputs are also added to sensitivity list

    always @*              // equivalent to always(a)
        my_or(a);          // b and c are not added to sensitivity list
endmodule

(20)List the predefined randomization methods.
Ans:-

randomize
pre_randomize
post_randomize

(19)What is scope randomization ?
Ans:-
Scope randomization ins SystemVerilog allows assignment of unconstrained or constrained random value to the variable within current scope

module MyModule;      
integer var, MIN;      

initial begin          
    MIN = 50;          
    for ( int i = 0;i<10 ;i++) begin              
        if( randomize(var) with { var < 100 ; var > MIN ;})  
            $display(" Randomization sucsessfull : var = %0d Min = %0d",var,MIN);   
        else                  
            $display("Randomization failed");
    end
          
    $finish;     
end
endmodule

Answers to SystemVerilog Interview Questions - 3

2009-08-25T10:19:00.000-07:00

(88)How to check weather a handles is holding object or not ?
Ans:-
It is basically checking if the object is initialized or not. In SystemVerilog all uninitialized object handles have a special value of null, and therefore whether it is holding an object or not can be found out by comparing the object handle to null. So the code will look like:-

usb_packet My_usb_packet; 
...
if(My_usb_packet == null) begin
    // This loop will get exited if the handle is not holding any object
    ....
end else begin
    // Hurray ... the handle is holding an object
    ...
end

(87)What is the difference between initial block and final block?
Ans:-
There are many difference between initial and final block. I am listing the few differences that is coming to mind now.

The most obvious one : Initial blocks get executed at the beginning of the simulation, final block at the end of simulation
Final block has to be executed in zero time, which implies it can't have any delay, wait, or non-blocking assignments. Initial block doesn't have any such restrictions of execution in zero time (and can have delay, wait and non-blocking statements)

Final block can be used to display statistical/genaral information regarding the status of the execution like this:-

final begin
    $display("Simulation Passed");
    $display("Final value of xyz = %h",xyz);
    $display("Bye :: So long, and Thanks for all the fishes");
end

(69)What is the difference between bits and logic?
Ans:-
bits is 2-valued (1/0) and logic is 4-valued (0/1/x/z)

(65)What is tagged union ?
Ans:-
An union is used to stored multiple different kind/size of data in the same storage location.

typedef union{
    bit [31:0]  a;
    int         b;
} data_u;

Now here XYZ union can contain either bit [31:0] data or an int data. It can be written with a bit [31:0] data and read-back with a int data. There is no type-checking done.

In the case where we want to enforce that the read-back data-type is same as the written data-type we can use tagged union which is declared using the qualifier tagged. Whenever an union is defined as tagged, it stores the tag information along with the value (in expense of few extra bits). The tag and values can only be updated together using a statically type-checked tagged union expression. The data member value can be read with a type that is consistent with current tag value, making it impossible to write one type and read another type of value in tagged union. (the details of which can be found in section 3.10 and 7.15 of SV LRM 3.1a).

typedef union tagged{
    bit [31:0]  a;
    int         b;
} data_tagged_u;

// Tagged union expression
data_tagged_u data1 = tagged a 32'h0;
data_tagged_u data2 = tagged b 5;

// Reading back the value
int xyz = data2.b;

(56)What is the need of alias in SV?
Ans:-
The Verilog has one-way assign statement is a unidirectional assignment and can contain delay and strength change. To have bidirectional short-circuit connection SystemVerilog has added alias statement. An excellent usage example of alias can be found out at http://www.systemverilog.org/pdf/SV_Symposium_2003.pdf(Slide # 59)

Few minor updates

2009-08-24T04:16:00.001-07:00

Two small updates from my blog.

My blog has started getting attentions from Verification community. Recently my blog got added to blogroll of VMM martial art blog (http://www.vmmcentral.org/vmartialarts/). Seems people are finding my blog worth reading/visiting. My blog is feeling blessed :)
With almost 4-5 hrs of effort I could make syntaxhighlighter work (with small minor hiccups). It took way too much time as compared to what I hoped for, but the end result of it is worth it. A sample o/p from syntax highlighter.

// Byte Pack
function int unsigned atm_cell::byte_pack(ref logic [7:0] bytes[],
                                          input int unsigned offset,
                                          input int kind);
   // Make sure there is enough room in the array
   if(bytes.size() < this.byte_size())
        bytes = new [this.byte_size()] (bytes);
   // Pack the bytes
   bytes[0] = {gfc, vpi[7:4]};
   bytes[1] = {vpi[3:0], vci[15:12]};
   bytes[2] = {vci[11:4]};
   bytes[3] = {vci[3:0], pt, clp};
   bytes[4] = {hec};
   for (int i=0; i < 48; i++)
     bytes[i+5]=payload[i];
   byte_pack = 53;
endfunction

// Byte Unpack
function int unsigned atm_cell::byte_unpack(const ref logic[7:0] bytes[],
                                            input int unsigned offset,
                                            input int len,
                                            input int kind);
   {gfc, vpi, vci, pt, clp, hec} = {bytes[0], bytes[1], bytes[2],
                                     bytes[3], bytes[4]};
   for (int i = 0; i != 48; ++i)
     payload[i] = bytes[i+5];

   return 53;
endfunction

All about fork-join of System Verilog

2009-08-21T10:24:00.000-07:00

I have added histstat hit counter for my blog to have an idea about traffic/visitor/search engine trends. One interesting I am observing is that quite a few hit to my site is coming for fork/join interview questions in Google. Hence I thought, why not have a real useful post on fork/join{x} of SystemVerilog and its associated disable/wait command.

Fork-join statement has come from Verilog. It is used for forking out parallel processes in test bench. SV substantially improved fork/join construct to have much more controllability in process creation, destruction, and waiting for end of the process.

The basic syntax of fork join block looks like this:

fork
   begin : First_thread
       // Code for 1st thread
   end
   begin : Second_thread
       // Code for 2nd thread
   end
   begin : Third thread
       // Code for 3rd branch
   end
   ...
join    // Can be join_any, join_none in SV

There are 3 different kind of join keyword in SV, each specifying a different way of waiting for completion of the threads/process created by the fork.

join : waits for completion of all of the threads
join_any : waits for the completion of the 1st thread, then comes out of fork loop, but lets the other process/thread execute as usual
join_none : doesn't wait for completion of any thread, just starts then and immediately exits fork loop.

Now, suppose you have exited the fork loop by join_none or join_any and after some steps, you want to wait till completion of all the threads spanned by the previous fork loop. SV has "wait fork" for the same.

Now, suppose you have exited the fork loop by join_none or join_any and after some steps, you want to kill all the threads spanned by the previous fork loop. SV has "disable fork" for the same.

Next interesting scenario: you have exited fork loop by join_none or join_any and after some steps, you want to kill just one thread (out of many). The solution, have named begin end block and call "disable ". (For example, in the last example if you want to kill only the 2nd thread after exiting the loop via join_any/join_none, then add "disable Second_thread;" at the point where you want to disable the second thread.

I have created a image to pictorially depict fork/join in SV. Hope that will help understand this in a much better way.

VMM shorthand macros

2009-08-20T09:48:00.001-07:00

Those who have worked with VMM based verification environment must have encountered situation where you need to code the different essential functions of vmm_data class like copy, psdisplay, compare and so on. This task become very tedious/boring when the number of classes you need to code is substantial, each having lengthy list of data member. Not long back, to get rid of the monotonicity of the above task, I sat for a day and wrote a perl script to generate the complete vmm_data class with essential functions from a class template.

Well, my one day effort is fixing the same is not worth the effort, as VMM has in-built short-hand-macros to solve it. It's especially useful when you don't have much non-standard data type (which are not supported by VMM shorthand macro)

class sample_class extends vmm_data;

// Simple scalar types
rand bit [7:0] da;
rand bit [8:0] db [10];
rand bit       dc [];
rand bit       dd [int];
rand bit       de [string];

...
‘vmm_data_member_begin(sample_class)
‘vmm_data_member_scalar(da, DO_ALL)         
‘vmm_data_member_scalar_array(db, DO_ALL)   
‘vmm_data_member_scalar_da(dc, DO_ALL)      
‘vmm_data_member_scalar_aa_scalar(dd, DO_ALL)
‘vmm_data_member_scalar_aa_string(de, DO_ALL)
‘vmm_data_member_end(sample_class)
...
endclass : sample_class

Some salient features of VMM shorthand macros are :

They can be used for {scalar, string, enums, vmm_data, handles} x {normal, array, dynamic array, associative array (scalar, and string type)} combination (Total 25 types)
These shorthands are valid for classes derived from vmm_data, vmm_env, vmm_subenv, vmm_xactor, and vmm_scenario
The function which will get implemented depends upon what class your class is being instantiated from.
For unlucky data member which doesn't fall into these 25 category, you can specify the same using `vmm_data_member_user_defined macro

What I have presented here is a very high level overview of the feature and in no way complete. For interested user please refer these links for complete details:-

Explain the difference between data types logic and reg and wire

2009-08-18T08:50:00.000-07:00

Ans:-
To answer this I am not assuming the reader knows the answer for the difference between wire and reg.

Wire:-

Wires are used for connecting different elements
They can be treated as a physical wire
They can be read or assigned
No values get stored in them
They need to be driven by either continuous assign statement or from a port of a module

Reg:-

Contrary to their name, regs doesn't necessarily corresponds to physical registers
They represents data storage elements in Verilog/SystemVerilog
They retain their value till next value is assigned to them (not through assign statement)
They can be synthesized to FF, latch or combinational circuit (They might not be synthesizable !!!)

Wires and Regs are present from Verilog timeframe. SystemVerilog added a new data type called logic to them. So the next question is what is this logic data type and how it is different from our good old wire/reg.

Logic:-

As we have seen, reg data type is bit mis-leading in Verilog. SystemVerilog's logic data type addition is to remove the above confusion. The idea behind having a new data type called logic which at least doesn't give an impression that it is hardware synthesizable
Logic data type doesn't permit multiple driver. It has a last assignment wins behavior in case of multiple assignment (which implies it has no hardware equivalence). Reg/Wire data type give X if multiple driver try to drive them with different value. Logic data type simply assign the last assignment value.

The next difference between reg/wire and logic is that logic can be both driven by assign block, output of a port and inside a procedural block like this

logic a;
assign a = b ^ c;                   // wire style 
always (c or d) a = c + d;          // reg style
MyModule module(.out(a), .in(xyz)); // wire style

Reference:-

SystemVerilog OOP links

2009-08-15T11:51:00.001-07:00

Here are some nice OOP links on SystemVerilog OOP which can be used as a good starting point/reference.

Object Oriented Programming for Hardware Verification

Improve Your SystemVerilog OOP Skills by Learning Principles and Patterns
SystemVerilog OOP OVM Feature Summary

SystemVerilog OOP Ovm Features Summary
View more presentations from Amal Khailtash.
Enhancing SystemVerilog with AOP Concepts (On how to mimic AOP features in OOP, good for guyz coming from e background)
Testbench.in OOP Tutorial

Answers to SystemVerilog Interview Questions - 2

2009-08-13T10:40:00.000-07:00

(86) What is the use of "extern"?
(66)What is "scope resolution operator"?

Ans:-
extern keyword allows out-of-body method declaration in classes. Scope resolution operator ( :: ) links method declaration to class declaration.

class XYZ;
// SayHello() will be declared outside the body 
// of the class
extern void task SayHello();
endclass : XYZ

void task XYZ :: SayHello();
$Message("Hello !!!\n");
endtask : SayHello

(76) What is layered architecture ?

Ans:-
In SystemVerilog based constrained random verification environment, the test environment is divided into multiple layered as shown in the figure. It allows verification component re-use across verification projects.

(71)What is the difference between $rose and posedge?

Ans:-
posedge return an event, whereas $rose returns a Boolean value. Therefore they are not interchangeable.

(64)What is "this"?

Ans:-
"this" pointer refers to current instance.

(38)Write a clock generator without using always block.

Ans:-

initial begin
   clk <= '0;
   forever #(CYCLE/2) clk = ~clk
end

(35)How to implement always block logic in program block ?
Ans:-

Use of forever begin end. If it is a complex always block statement like always (@ posedge clk or negedge reset_)

always @(posedge clk or negedge reset_) begin
   if(!reset_) begin
       data <= '0;
   end else begin
       data <= data_next;
   end
end

// Using forever : slightly complex but doable
forever begin
   fork
   begin : reset_logic
       @ (negedge reset_);
       data <= '0;
   end : reset_logic
   begin : clk_logic
       @ (posedge clk);
       if(!reset_)    data <= '0;
       else           data <= data_next;
   end : clk_logic
   join_any
   disable fork
end

Answers to SystemVerilog Interview Questions - I

2009-08-12T10:37:00.000-07:00

Posting answers to few System Verilog Questions (Please refer System Verilog Interview Questions for questions)

10> What is the need of virtual interface ?
Ans:-
An interface encapsulate a group of inter-related wires, along with their directions (via modports) and synchronization details (via clocking block). The major usage of interface is to simplify the connection between modules.

But Interface can't be instantiated inside program block, class (or similar non-module entity in SystemVerilog). But they needed to be driven from verification environment like class. To solve this issue virtual interface concept was introduced in SV.

Virtual interface is a data type (that implies it can be instantiated in a class) which hold reference to an interface (that implies the class can drive the interface using the virtual interface). It provides a mechanism for separating abstract models and test programs from the actual signals that make up the design. Another big advantage of virtual interface is that class can dynamically connect to different physical interfaces in run time.

For more details please refer the following links

18> What is difference between $random() and $urandom()
Ans:-

$random system function returns a 32-bit signed random number each time it is called
$urandom system function returns a 32-bit unsigned random number each time it is called. (newly added in SV, not present in verilog)

47> How to randomize dynamic arrays of an object
Ans:-

class ABC;
// Dynamic array
rand bit [7:0] data [];

// Constraints
constraint cc {
// Constraining size
data.size inside {[1:10]};

// Constraining individual entry
data[0] > 5;

// All elements
foreach(data[i])
if(i > 0)
data[i] > data[i-1];
}
endclass : ABC

Event Region, Scheduling Semantics in System Verilog

2009-08-11T07:56:00.000-07:00

Let me start the post by asking one commonly asked interview question in verilog/system-verilog, that is what is the output of the following block

always @(posedge clk) begin
   a = 0;
   a <= 1;
   $display(s);
end

To begin with let me be clear that this is not the correct way to code in verilog/SV. One shouldn't mix blocking and non-blocking assignment in the same begin-end block. But this question is asked to check the knowledge of scheduling semantics of verilog/SV.

Verilog scheduling semantics basically imply a four-level deep queue for the current simulation time:-

Active Events (blocking assignment, RHS of NBA, continuous assignment, $display, ...)
Inactive Events (#0 blocking assignment)
Non-Blocking Assign Updates (LHS of NBA)
Monitor Events ($monitor, $strobe).

Which implies, a=0 will be get printed in this example.

System Verilog has added few more level queue for simulation, the details of which can be found in these 2 excellent link on scheduling semantics of SV.

The Hitchhiker series on Verification - From Mentor Graphics

2009-08-10T09:33:00.000-07:00

It seems I am not the 1st one to have the Hichhiker series on SV-VMM. Back from 2007 time frame Mentor has a series of talk on System Verilog/AVM which is named as "The Hitchhiker Guide to XYZ". The good thing about these talks is that you don't need to register for watching these videos (almost all of the rest multimedia needs a registration for watching them). These are the links for your viewing and Learning:-

What is Factory Pattern

2009-08-08T07:28:00.000-07:00

If you are working in System Verilog/VMM environment, it is high likely that you will be bombarded with word/expression from OOP world like "Factory Pattern", "Facade Pattern", "Observer Pattern" and so on. There is a finite possibility that you will seat down and start thinking what does those word mean and why they were used too frequently. Let me try to explain the idea/concept behind such word in the simplest way possible.

In SW engineering, a design pattern (or simply pattern) means a general repeatable solution to a commonly occurring problem. Most of these patterns have similarity to something or other in human society and hence they are known by that name.

Factory pattern as the name suggest, is aimed at solving the issue of creation of object. (Factory pattern is not the only pattern to deal with creation of objects, there are a bunch of more patterns for handling different kind of cases, and collectively they are known a creational patterns)

Let me give an example of case where we might need to use creational pattern and how to do so it in SV. Suppose you want to create a "Toy Factory" class which needs to create multiple types of toys (say toy aeroplane, toy tank, toy bus) depending upon the string input to it.

To create these different types of toys we need to have class defined for them. And there will be common method and data interface for these classes, hence it make sense to put all the common data member/task/functions in a class called toy class and then extend it.

class TOY;
// Common data memeber
string type;

// Common methods
 virtual function string get_type();
endclass : TOY

class TOY_Tank extends TOY;
function new();
   this.string = "Toy Tank";
endfunction : new

string function string get_type();
   return this.string;
endfunction : get_type
endclass : TOY_Tank

class TOY_Bus extends TOY;
function new();
   this.string = "Toy Bus";
endfunction : new

string function string get_type();
   return this.string;
endfunction : get_type
endclass : TOY_Bus

class TOY_factory;
Toy my_toy

// Common methods
function toy get_toy(int type);
  if(type == 1) this.my_toy = new TOY_Tank();
  if(type == 2) this.my_toy = new TOY_Bus();
  return this.my_toy;
endfunction : get_toy
endclass : TOY_factory

Note that we are using virtual function for bringing polymorphism in action and save us from having an individual instance of the toy type in the factory class.

Reference

Factory Method Design Pattern from sourcemaking.com
Factory Method Pattern from wikipedia
Factory Pattern from JAVA design pattern

System Verilog Interview Questions

2009-08-07T09:57:00.000-07:00

System Verilog Interview questions from http://www.edaboard.com/ftopic315416.html. I don't know answers to all of the questions, but will try to find out their answer from internet (thanks to the all powerful Google) and post the answers in this blog (one by one most likely). If you know answers to any of these then you are well come to share the same by commenting to this post.

What is callback ?
What is factory pattern ?
Explain the difference between data types logic and reg and wire
What is the need of clocking blocks ?
What are the ways to avoid race condition between testbench and RTL using SystemVerilog?
Explain Event regions in SV.
What are the types of coverages available in SV ?
What is OOPS?
What is inheritance and polymorphism?
What is the need of virtual interfaces ?
Explain about the virtual task and methods .
What is the use of the abstract class?
What is the difference between mailbox and queue?
What data structure you used to build scoreboard
What are the advantages of linkedlist over the queue ?
How parallel case and full cases problems are avoided in SV
What is the difference between pure function and cordinary function ?
What is the difference between $random and $urandom?
What is scope randomization
List the predefined randomization methods.
What is the dfference between always_combo and always@(*)?
What is the use of packagess?
What is the use of $cast?
How to call the task which is defined in parent object into derived class ?
What is the difference between rand and randc?
What is $root?
What is $unit?
What are bi-directional constraints?
What is solve...before constraint ?
Without using randomize method or rand,generate an array of unique values?
Explain about pass by ref and pass by value?
What is the difference between bit[7:0] sig_1; and byte sig_2;
What is the difference between program block and module ?
What is final block ?
How to implement always block logic in program block ?
What is the difference between fork/joins, fork/join_none fork/join_any ?
What is the use of modports ?
Write a clock generator without using always block.
What is forward referencing and how to avoid this problem?
What is circular dependency and how to avoid this problem ?
What is cross coverage ?
Describe the difference between Code Coverage and Functional Coverage Which is more important and Why we need them
How to kill a process in fork/join?
Difference between Associative array and Dynamic array ?
Difference b/w Procedural and Concurrent Assertions?
What are the advantages of SystemVerilog DPI?
How to randomize dynamic arrays of objects?
What is randsequence and what is its use?
What is bin?
Why always block is not allowed in program block?
Which is best to use to model transaction? Struct or class ?
How SV is more random stable then Verilog?
Difference between assert and expect statements?
How to add a new processs with out disturbing the random number generator state ?
What is the need of alias in SV?
What is the need to implement explicitly a copy() method inside a transaction , when we can simple assign one object to other ?
How different is the implementation of a struct and union in SV.
What is "this"?
What is tagged union ?
What is "scope resolution operator"?
What is the difference between Verilog Parameterized Macros and SystemVerilog Parameterized Macros?

What is the difference between

logic data_1;
var logic data_2;
wire logic data_3j;
bit data_4;
var bit data_5;

What is the difference between bits and logic?
Write a Statemechine in SV styles.
What is the difference between $rose and posedge?
What is advantage of program block over clockcblock w.r.t race condition?
How to avoid the race condition between programblock ?
What is the difference between assumes and assert?
What is coverage driven verification?
What is layered architecture ?
What are the simulation phases in your verification environment?
How to pick a element which is in queue from random index?
What data structure is used to store data in your environment and why ?
What is casting? Explain about the various types of casting available in SV.
How to import all the items declared inside a package ?
Explain how the timescale unit and precision are taken when a module does not have any timescalerdeclaration in RTL?
What is streaming operator and what is its use?
What are void functions ?
How to make sure that a function argument passed has ref is not changed by the function?
What is the use of "extern"?
What is the difference between initial block and final block?
How to check weather a handles is holding object or not ?
How to disable multiple threads which are spawned by fork...join

What is this "System Verilog Callback"

2009-08-05T11:14:00.000-07:00

Callback is one of the major confusing point for a System Verilog learner. Many people have asked the same question in many forums, but the answer doesn't seems to satisfy fully the quest of the person who has raised the querry. I too had the same issue, but I learned it slowly in a hard way. I am presenting here a way in which if I had an answer, I would have learned faster.

We can pass data member to any function. Now consider a case where you are passing a function (say func1) as a data member to another function (say func2) and you get what is called callback. The reason why it is called callback is that the function func2 now can call anywhere in its code function func1.

From wikipedia

In computer programming, a callback is executable code that is passed as an argument to other code. It allows a lower-level software layer to call a subroutine (or function) defined in a higher-level layer.

Note that SV doesn't give a straight-forward way of passing a function as argument for another function. But we can get the same result (almost we can say!) by using OOP. The idea is to describe all the functions (both func1 type and func2 type) in a base class (don't implement the funct2 kind of function and make them virtual for polymorphism), and then extend the class to a derived class where you implement the func2 type of function.

Example:-

class abc_transactor;
virtual task pre_send(); endtask
virtual task post_send(); endtask

task xyz();
  // Some code here
  this.pre_send();
  // Some more code here
  this.post_send();
  // And some more code here
endtask : xyz
endclass : abc_transactor

class my_abc_transactor extend abc_transactor;
virtual task pre_send();
  ...     // This function is implemented here
endtask

virtual task post_send();
  ...     // This function is implemented here
endtask

endclass : my_abc_transactor

Now let me explain how it is going to work. The base class abc_transactor has 3 tasks, 2 of which are declared virtual and are not implemented. But they are being called from another task xyz() which is fully implemented. The unimplemented virtual task are called callback class.

The child class, which extends from the base class, implements the previous unimplemented tasks. It inherits the xyz() task from the base class and hence doesn't need to change it. By this we can inject executable code to a function without modifying it.

Now the next question is why is done. There are many reasons for it.

The biggest advantage is that you can modify the behavior of task xyz() without modifying it in the base or child class. It is a big advantage as no one wants to fiddle with known good functioning code.
Consider a case where you are writing a base class which is going to be used by multiple test environment, and for each test environment a known part of the code, or a known function/task is going to change. The natural choice is to implement those change-in-every-case functions/tasks as callback method and let the user extend your base class with specifying only that part of the code which need to be changed in his case.

Simple callback using the above approach does have some known limitations, which can be solved using design patterns (from OOP land), the details of which can be found at Janik's article of vmm_callback.

Reference:-

System Verilog Gotchas - by Stuart Sutherland

2009-08-02T07:48:00.000-07:00

In one of my last post I have added one of the System Verilog Gotcha paper. There are 2 more System Verilog Gotcha presentations (this time by Stuart Sutherland).

The compete presentation/papers of Stuart on System Verilog, Verification, Verilog can be viewed at http://www.sutherland-hdl.com/papers-by-sutherland.php

System Verilog LRM

2009-08-01T10:02:00.000-07:00

System Verilog LRM, as the name suggest, is the definite reference manual for SV. Unlike other standard reference manual, which are too academic or boring to read, this one is a easy to use, easy to read and has large number of examples. The link of which can be easily got by a simple google search.

http://www.vhdl.org/sv/SystemVerilog_3.1a.pdf

There is another reference manual or standard for SV (IEEE 1800) which is pretty much same as the LRM, and you have to pay for downloading it (assuming your organization don't pay $$$ to IEEE for free access to its huge papers and standards)

Best sites to Learn System Verilog

2009-07-31T03:56:00.001-07:00

There are large numbers of sites which have materials of system verilog, reading which you can learn it. But, there are few really good site, where system verilog has been described in a real nice way, and you have a smooth ride while learning SV. I personally learned from them quite a bit of system verilog from these sites.

Testbench.in : System Verilog and VMM tutorial with a lots of example
Asicguru.com : Another nice SV tutorial site
Doulos SV Tutorial : Not that much extensive, but still good
Another decent tutorial from Project-Veripage
SV Tutorial from ASIC-World. It is not yet complete, but once it is complete, then it will be another great site to learn SV.

Amongst all 4, testbench.in is the best. It's a 10/10 site, you visit it, start learning and will fall in love with it. I feel proud of the fact that the creator of the site Gopi Krishna is from India. Way to go Gopi.

System Verilog Gotcha by Shalom Bresticker

2009-07-30T08:07:00.000-07:00

Return of the SystemVerilog Gotchas.bresticker

SV Tips/Tricks - Converting Strings to Enums

2009-07-29T06:04:00.000-07:00

SystemVerilog enumerated data type has one major shortcoming namely the inability to covert string to enum data type, whereas the reverse is possible. But there are many cases when one find the need to do so. Thankfully JL Gray of verilab has created a sample class template which can be used for the same purpose. The link to the blog entry is

http://www.verilab.com/blog/2007/10/casting-strings-to-enums-in-systemverilog/

Enjoy maadi !!

A Presentation on System Verilog Assertion

2009-07-28T12:48:00.000-07:00

Introduction to System Verilog Assertions -

System Verilog Basic Links

2009-07-28T12:17:00.000-07:00

These days I am working on System Verilog/VMM (for those lucky one who don't know what these are, System Verilog is a Hardware Verification Language which is used for verifying complex multi-million gates digital designs, and VMM is a verification methodology for the same):-

Presentations:-

Welcome

2009-07-28T11:42:00.001-07:00

Welcome to the new blog