The Ultimate Hitchhiker's Guide to Verification

Dumping ground of useful links/articles/tips/tricks on System Verilog/VMM/OVM as and when I stumble upon them and some of my views on it :)

Slides from DVCon UK 2011

Pointer to UPF standard online

 UPF 1.0 standard
UPF 2.0 standard via scribd. Can be viewed online.

A nice blog on Power Aware Verification/UPF

Today I came across a nice blog on UPF/Low Power. Sharing it

Mentor Graphics NOIDA is hiring.

Please mail me your resume at subash.nayak@gmail.com if you want to apply to any of the below jobs.

One small update

Hi all,

To begin with let me thank all for visiting my blog. I have got many feedback on how people (few whom I know personally, and many I don't know) have used my blog for learning SV and preparing for job interviews. It feel good knowing that I have contributed something positively (a very little, I know :)) to the society via my blog. 

There is a small news to share with you all. Recently I have joined Mentor Graphics NOIDA as LMTS, where I am involved in tool development effort. So it is hardcore C++ coding/debug for me, and very little SystemVerilog/Verification. So from now on I am planning to blog on C/C++/SW development mostly, little less SV.

Regards,
-Subash

Wavedrom : Web based Waveform editor

Few nice articles on UVM

Easier UVM for Functional Verification by Mainstream Users :: From Doulos

How Do I Get Environment Variable into a String in SystemVerilog


From Synopsys Solvnet, Needs to have Solvnet id, seems to be specific to VCS



About Me

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I am from Sambalpur, Orissa, India. Have done Btech and Mtech in ECE from IIT Kharagpur. Currently working as Lead Member Technical Staff at Mentor Graphics Noida

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