The Ultimate Hitchhiker's Guide to Verification

Dumping ground of useful links/articles/tips/tricks on System Verilog/VMM/OVM as and when I stumble upon them and some of my views on it :)

System Verilog `define macros : Why and how to use them (and where not to use!!!)

I most confess, I have become a very big fan of SystemVerilog `define macro for the amount of effort I save because of using it. The big advantage of using this is that you can concisely describe your intention in a more readable (and less SystemVerilog syntax) using macro. Another advantage is you need to change only at one place if you find out that you need to change the expression you have used in 100 of places. The 3rd reason is that it is widely used in industry. Some example worth quoting are

  1. Using SystemVerilog Assertions for Functional Coverage
  2. Using SystemVerilog Assertions for Creating Property-Based Checkers
  3. SystemVerilog Assertions Design Tricks and SVA Bind Files
  4. VMM and especially VMM data macro
Next question : Where shall I get the required info on how to use SystemVerilog `define macro
Ans : Web (thanks to the all powerful demi-god of internet ... Google)
  1. http://www.google.co.in/#hl=en&safe=off&q=Systemverilog+Macro 
  2. System Verilog LRM 3.1a : Section : 25.2
  3. Sandeep Vaniya's Advanced Use of define macro in SystemVerilog (not so advanced actually !!!)
From reading these it might be apparent that define macro can be used for adding a postfix to the variable, but not prefix. I was thinking the same after reading the description (they don't have a single example of adding prefix to the variable via `define. Confused ?? Let me explain by giving a concrete example

// Example macro for a coverage class
// Aim : want to get ABC_cp : coverpoint ABC {bins b = {1}; }
// by calling `COV(ABC)
`define COV(__name) __name``_cp : coverpoint __name {bins b = {1}; }

// Next
//     What to do if I want cp_ABC in place of ABC_cp as for the above example
//     NOTE : I can't use cp_``__name as cp_ is not an input to the macro

// Solution
//     Use nested macros
`define PREFIX(__prefix, __name) __prefix``__name
`define COV2(__name) `PREFIX(cp_,__name) : coverpoint __name {bins b = {1}; }

Nested macro is not a new thing in SV. They are being extensively used in VMM data macro class. But no example of nested macro and achieving of addition pre_fix to variable name in `define macro is bit puzzling to me. I tried the above in vcs and seems to work perfectly fine.

Next, where not to use `define (SV other better alternatives to `define these cases)
  1. New Verilog-2001 Techniques for Creating Parameterized Models (or Down With `define and Death of a defparam!): Bit old but still usefull

Answers to SystemVerilog Interview Questions - 8

13. What is the difference between mailbox and queue?
Ans:-
Mailbox are FIFO queue, which allows only atomic operations. They can be bounded/unbounded. A bounded mailbox can suspend the thread (while writing if full, while reading if empty) via get/put task. Thats why mailbox is well suited for communication between threads.

24. What is the use of $cast?
Ans:-
Typecasting in SV can be done either via static casting (', ', ') or dynamic casting via $cast task/function. $cast is very similar to dynamic_cast of C++. It checks whether the casting is possible or not in run-time and errors-out if casting is not possible.

27. What is $unit?
Ans:-
Refer these 2 doc form more details

  1. http://www.systemverilog.org/pdf/SystemVerilog_Overall_31A.pdf 
  2. SV LRM 3.1a :: Section 18.3

28 .What are bi-directional constraints?
Ans:-
Constraints by-default in SystemVerilog are bi-directional. That implies that the constraint solver doesn't follow the sequence in which the constraints are specified. All the variables are looked simultaneously. Even the procedural looking constrains like if ... else ... and -> constrains, both if and else part are tried to solve concurrently. For example (a==0) -> (b==1) shall be solved as all the possible solution of (!(a==0) || (b==1)).

29. What is solve...before constraint ?
Ans:-
In the case where the user want to specify the order in which the constraints solver shall solve the constraints, the user can specify the order via solve before construct. i.e.

...
constraint XYZ  {
    a inside {[0:100]|;
    b < 20;
    a + b > 30;
    solve a before b;
}

The solution of the constraint doesn't change with solve before construct. But the probability of choosing a particular solution change by it.

40. What is circular dependency and how to avoid this problem ?
Ans:-
Over specifying the solving order might result in circular dependency, for which there is no solution, and the constraint solver might give error/warning or no constraining. Example

...
int x, y, z;
constraint XYZ  {
    solve x before y;
    solve y before z;
    solve z before x;
    ....
}

Answers to SystemVerilog Interview Questions - 7

4. What is the need of clocking blocks ?
Ans:-
Clocking block in SystemVerilog are used for specifying the clock signal, timing, and synchronization requirements of various blocks. It separates the timing related information from structural, functional and procedural element of the TB. There are quite a few links on clocking block in the internet. These are links to learn about SV clocking blocks.

  1. AsicGuru :: To the point answer on the need of clocking block
  2. Testbench.in :: Clocking block  
  3. ProjectVeripage :: Clocking block 
  4. Doulos :: Clocking block 
  5. Asicworld :: Clocking block
  6. SystemVerilog Event Regions, Race Avoidance & Guidelines

 5. What are the ways to avoid race condition between testbench and RTL using SystemVerilog?
Ans:-
Short answer : -
  1. Program  block
  2. Clocking block
  3. Enforcement of design signals being driven in non-blocking fashion from program block
Long answer :-
Too long to describe here :). Please refer these doc/sections for more idea/info
  1. Section 16.4 of SV LRM
  2. http://www.testbench.in/SV_24_PROGRAM_BLOCK.html
  3. http://www.sunburst-design.com/papers/CummingsSNUG2006Boston_SystemVerilog_Events.pdf 
  4. VG discussion of the necessity of program block. 

7. What are the types of coverages available in SV ?
Ans:-
Using covergroup : variables, expression, and their cross
Using cover keyword : properties

12. What is the use of the abstract class?
Ans:-

Answers to SystemVerilog Interview Questions - 6

(30)Without using randomize method or rand,generate an array of unique values?
Ans:-

...
int UniqVal[10];
foreach(UniqVal[i]) UniqVal[i] = i;
UniqVal.shuffle();
...

(32)What is the difference between byte and bit [7:0]?
Ans:-
byte is signed whereas bit [7:0] is unsigned.

(33)What is the difference between program block and module?
Ans:-
Program block is newly added in SystemVerilog. It serves these purposes
  1. It separates testbench from DUT
  2. It helps in ensuring that testbench doesn't have any race condition with DUT
  3. It provides an entry point for execution of testbench
  4. It provides syntactic context (via program ... endprogram) that specifies scheduling in the Reactive Region.
Having said this the major difference between module and program blocks are
  1. Program blocks can't have always block inside them, modules can have.
  2. Program blocks can't contain UDP, modules, or other instance of program block inside them. Modules don't have any such restrictions.
  3. Inside a program block, program variable can only be assigned using blocking assignment and non-program variables can only be assigned using non-blocking assignments. No such restrictions on module
  4. Program blocks get executed in the re-active region of scheduling queue, module blocks get executed in the active region
  5. A program can call a task or function in modules or other programs. But a module can not call a task or function in a program.
More details:-
  1. http://www.testbench.in/SV_24_PROGRAM_BLOCK.html 
  2. http://www.project-veripage.com/program_blocks_1.php and few more next/next !!!
  3. Section 16, SystemVerilog LRM 3.1a ... It's worth the effort reading line-by-line (and between the lines if you can :) ).
(37)What is the use of modports?
Ans:-
Modports are part of Interface. Modports are used for specifing the direction of the signals with respect to various modules the interface connects to.

...
interface my_intf;
    wire x, y, z;
    modport master (input x, y, output z);
    modport slave  (output x, y, input z);
endinterface

Please refer section 19.4 of SV LRM for more details

11. Explain about the virtual task and methods .
Ans:-
See http://www.testbench.in/CL_07_POLYMORPHISM.html

Answers to SystemVerilog Interview Questions - 5

(9)What is inheritance and polymorphism?
 Please refer these links for more details on inheritance/polymorphism.

  1. http://www.testbench.in/CL_00_INDEX.html
  2. SV OOP Links
(14)What data structure you used to build scoreboard?
Ans:-
Queue

(16)How parallel case and full cases problems are avoided in SV ?
 Ans:-
See Page 34/35 of http://www.systemverilog.org/pdf/SV_Symposium_2003.pdf

(22)What is the use of package?
 Ans:-
In Verilog declaration of data/task/function within modules are specific to the module only. They can't be shared between two modules. Agreed, we can achieve the same via cross module referencing or by including the files, both of which are known to be not a great solution.

The package construct of SystemVerilog aims in solving the above issue. It allows having global data/task/function declaration which can be used across modules. It can contain module/class/function/task/constraints/covergroup and many more declarations (for complete list please refer section 18.2 of SV LRM 3.1a)

The content inside the package can be accessed using either scope resolution operator (::), or using import (with option of referencing particular or all content of the package).

package ABC;
    // Some typedef
    typedef enum {RED, GREEN, YELLOW} Color;

    // Some function
    void function do_nothing()
        ...
    endfunction : do_nothing

    // You can have many different declarations here
endpackage : ABC

// How to use them
import ABC::Color;     // Just import Color
import ABC::*;         // Import everything inside the package

(26)What is $root?
 Ans:-
$root refers to the top level instance in SystemVerilog

package ABC;
$root.A;       // top level instance A
$root.A.B.C;   // item C within instance B within top level instance A

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I am from Sambalpur, Orissa, India. Have done Btech and Mtech in ECE from IIT Kharagpur. Currently working as Lead Member Technical Staff at Mentor Graphics Noida

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