4. What is the need of clocking blocks ?
Clocking block in SystemVerilog are used for specifying the clock signal, timing, and synchronization requirements of various blocks. It separates the timing related information from structural, functional and procedural element of the TB. There are quite a few links on clocking block in the internet. These are links to learn about SV clocking blocks.
- AsicGuru :: To the point answer on the need of clocking block
- Testbench.in :: Clocking block
- ProjectVeripage :: Clocking block
- Doulos :: Clocking block
- Asicworld :: Clocking block
- SystemVerilog Event Regions, Race Avoidance & Guidelines
5. What are the ways to avoid race condition between testbench and RTL using SystemVerilog?
Short answer : -
- Program block
- Clocking block
- Enforcement of design signals being driven in non-blocking fashion from program block
Too long to describe here :). Please refer these doc/sections for more idea/info
- Section 16.4 of SV LRM
- VG discussion of the necessity of program block.
7. What are the types of coverages available in SV ?
Using covergroup : variables, expression, and their cross
Using cover keyword : properties
12. What is the use of the abstract class?